Abstract: A method of manufacturing a stacked capacitor. A first dielectric layer is formed over a substrate. A first nitride layer is formed on the first dielectric layer. A storage node contact hole is formed to penetrate through the first nitride layer and the first dielectric layer and to expose a portion of the substrate. A first conductive plug is formed in the storage node contact hole. A second dielectric layer is formed on the first nitride layer and the first conductive plug. A second nitride layer is formed on the second dielectric layer. A contact hole is formed to penetrate through the second nitride layer and the second dielectric layer and to expose portions of the first conductive plug. A second conductive plug is formed in the contact hole with a surface level lower than a surface level of the second nitride layer. A metal barrier layer is formed on the second conductive plug and fills the contact hole. A first metal layer is formed over the substrate.

Abstract: A method for manufacturing an integrated circuit capacitor is provided in the present invention. First, a semiconductor substrate is etched to form a contact hole. A polysilicon contact is then formed to fill into the contact hole. A metal layer is formed on the substrate and the polysilicon contact. Next, a silicon catching layer is formed on the metal layer. An annealing step is performed to substitute the silicon contact with a portion of said metal layer for forming a metal contact, wherein the silicon atom are driven to react with the silicon catching layer for forming a compound layer underneath the silicon catching layer. After the metal layer, the silicon catching layer and the compound layer are removed, the first conduction layer is formed on the substrate and the metal contact to serve as a bottom electrode. Then, a dielectric layer is formed along the surface of the first conduction layer. The second conduction layer is next formed on the dielectric layer to serve as a top electrode.

Abstract: The method for forming inter-metal dielectric layers in a metallization process mainly includes the following steps. At first, a semiconductor substrate having interconnection structures formed thereon is provided. A liner layer is formed to cover the interconnection structures and the substrate, and a first dielectric layer is formed on the liner layer. A planarization stop layer is formed on the first dielectric layer and a second dielectric layer is formed on the planarization stop layer, wherein the second dielectric layer has a higher removal rate than the planarization stop layer in a planarization process. Finally, the substrate is planarized by removing portions of the second dielectric layer until portions of the planarization stop layer is presented.

Abstract: A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

Abstract: The present invention discloses a structure of metal interconnection lines in integrated circuits for improving thermal conductivity therein. In the structure, a silicon nitride layer is formed underneath a first metal pattern of integrated circuits. Moreover, a silicon nitride plug is formed between two adjacent metal patterns and it serves as a thermal conductor. At least one metal plug in dielectric layers between the metal patterns is an electrical connection of integrated circuits. The present invention also discloses a method for fabricating the structure as mentioned above.

Abstract: A method of manufacturing a deep trench capacitor. A first silicon oxide layer is formed on a substrate. A first trench is formed in the substrate. A rugged polysilicon layer is formed on the surface of the first trench. The grains of the rugged polysilicon layer are distributed discretely on surface of the first trench. A second silicon oxide layer is formed on the rugged polysilicon layer. The exposed substrate in the first trench is etched, in order to form a plurality of second trenches in the substrate of the first trench. The first and second silicon oxide layer are removed. A first conductive layer is formed over the substrate and conformal to the first trench and the second trenches. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

Abstract: The present discloses a method of forming shallow trench isolation to prevent the dishing effect, the corner effect and provide an effective endpoint detection. The method includes these steps below. A pad oxide layer is formed on a semiconductor substrate. A first silicon nitride layer is formed on the pad oxide layer. A trench is formed in the substrate. A liner layer is formed on sidewalls and a bottom of the trench. A second silicon nitride layer is formed on the first silicon nitride layer and the liner layer. A polysilicon layer is formed on the second silicon nitride layer. A first silicon dioxide layer is formed on said polysilicon layer, thereby filling the trench with the first silicon dioxide layer. The first silicon dioxide layer is polished by performing a chemical mechanical polishing with a poly slurry. The polysilicon layer is oxidized to form a second silicon dioxide layer. The first silicon nitride layer and the second silicon nitride layer are removed.

Abstract: A method for fabricating DRAM capacitor dielectric layer with high permittivity is disclosed. In the first preferred embodiment, the process temperature is about 700° C. or below. Thus this embodiment is apt to utilize for DRAM with metal silicide transistor. In the processes, the multiple thin silicon nitride layers are formed on respective film surface to obtain pinhole defects unmatched dielectric layer. The second preferred embodiment, the processes uses different CVD method to deposit multiple thin silicon nitride layers and thus pinhole defects are unmatched. Both of two embodiments provide capacitor dielectric layer with least leakage current so as to increase the capacitance.

Abstract: A multi-exposure process. By performing the multi-exposure process, the size of the line width can be enlarged or shrunk by the precondition of the fixed pitch. Moreover, the line width can be shrunk to a level even smaller than the resolving power of the stepper or the scanner. Additionally, by using the invention, the exposure energy, the exposure time and the exposure DOF can be fixed while the exposure process is performed. Therefore, the process window is increased and the yield is enhanced. Furthermore, the processing sequence according to the invention is simpler than the conventional photolithography processing sequence, so that the throughput can be increased.

Abstract: A method for fabricating a metal interconnect structure. A first insulating layer and a second insulating layer with a low dielectric constant are formed on a substrate in sequence. An opening is formed in the second insulating layer. A compact and high density third insulating layer is formed on the second insulating layer and in the opening to protect the second insulating layer from being damaged in a subsequent process for removing a photo-resist layer. A contact window is then formed in the third insulating layer at a bottom of the opening and the first insulating layer, so that a dual damascene opening is formed. The dual damascene opening is filled with metal with low resistivity to form the metal interconnect.

Abstract: A method of forming a planar interlayer dielectric layer over underlying structures is disclosed. First, a liner oxide layer is formed over the underlying structures. Then, a BPSG layer is formed over the liner oxide layer. The BPSG layer is polished and a cap oxide layer is formed over the BPSG layer. Finally, a nitride layer is formed over the cap oxide layer.

Abstract: A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

Abstract: A method for stacked capacitor. The method utilizes a silicon nitride layer as an etching stop layer for removing the insulation layer on each side of a crown-shaped capacitor structure. As soon as the insulation layer is removed the silicon nitride layer is removed as well. In addition, a high-temperature oxide layer is formed over the inter-layer dielectric. The high-temperature oxide layer can prevent the formation of hemispherical grains on its surface when selective hemispherical grains are formed on the surface of an amorphous silicon layer.

Abstract: A method for manufacturing stacked capacitor. The method utilizes a manufacture method of a trench line and a via applied in dual damascene process to form a trench line and a via in a dielectric layer. Then, multi-amorphous silicon layers with different doping concentration are conformally formed on an exposed surface of the trench line and the via to serve as a bottom electrode of a double-sided double-crown-shaped capacitor. Furthermore, a phosphine (PH3) treatment process is performed after hemispherical grains are formed on the bottom electrode of the double-sided double-crown-shaped capacitor to increase the doping concentration of the bottom electrode surface of the capacitor. Moreover, a poly slurry having a high polishing selectivity of amorphous silicon to silicon nitride is used in a chemical mechanical polishing process during the formation of the double-sided double-crown-shaped capacitor to promote good uniformity of the polished wafer and make the polish end point available.

Abstract: The method includes forming a metal layer over a substrate. Subsequently, a discrete dot masking is deposited on the surface of the metal layer. A discrete rugged polysilicon or hemispherical grained silicon (HSG-Si) can be chosen as the discrete dot masking. The source gas used to form the discrete rugged polysilicon includes Si2H6 at a temperature of about 400 to 450° C. An anisotropically etching step is performed to etch the metal layer by using the discrete dot masking as an etching mask, thereby forming a surface pattern formed thereon. Then, the discrete dot masking is removed. The metal layer is patterned to a conductive line pattern. An organic material layer with low dielectric constant is formed on the patterned metal layer. A silicon oxide layer is successively formed on the organic material layer, followed by polishing the silicon oxide layer using a chemical mechanical polishing (CMP).

Abstract: A method of fabricating a shallow trench isolation (STI). The method forms a spin-on glass layer after removing a pad oxide layer in a STI process in order to fill a cavity formed in an oxide layer in the vicinity of an interface between a STI and a substrate. Then, a planarization process is performed, and the spin-on glass layer is annealed into an oxide layer with good thermal stability.

Abstract: The method for forming a capacitor in the present invention includes the steps as follows. At first, a multi-layer structure is formed on a semiconductor substrate, and the multi-layer structure is provided to have etching selectivity in etching neighboring layers in the multi-layer structure. A top dielectric layer is then formed on the multi-layer structure. A first opening is defined in the top dielectric layer, and a second opening is defined in the multi-layer structure under the first opening. Next, a wet etch is performed through the second opening to form at least two lateral openings in the multi-layer structure. Following the wet etch, a first conductive layer is formed conformably on the top dielectric layer, on sidewalls of the first opening and the second opening, and filled within the at least two lateral openings. A filling layer is then formed on the substrate, and the filling layer and the first conductive layer on the top dielectric layer are removed.

Abstract: A structure and method of fabricating a stacked capacitor which forms a hemispherical grain (HSG) polysilicon on the surface of a crown shaped amorphous silicon layer. By selective tungsten deposition, the HSG polysilicon and the amorphous silicon layer are displaced with a rough tungsten layer. A material with a high dielectric constant and a metal layer are formed in sequence as a dielectric layer and an upper electrode of the capacitor, so as to form a crown metal-insulator-metal (MIM) capacitor.

Abstract: A method for forming a bottom storage node of a capacitor for a DRAM memory cell on a substrate is disclosed.

Abstract: A method of making a capacitor over a contact. The method comprises the steps of: (a) depositing an oxide layer over said contact; (b) forming a dual damascene opening in said oxide layer over said contact; (c) depositing a layer of insitu doped polysilicon over said dual damascene opening and said oxide layer; (d) depositing a layer of undoped amorphous polysilicon over said layer of insitu doped polysilicon; (e) removing said layer of undoped amorphous polysilicon and said layer of insitu doped polysilicon that is outside of said dual damascene opening; (f) removing said oxide layer to leave a dual damascene structure comprising insitu doped polysilicon and undoped amorphous polysilicon; (g) forming hemispherical grain (HSG) polysilicon on the surface of said dual damascene structure; (h) forming a dielectric layer over said dual damascene structure; and (i) forming a top electrode over said dielectric layer.