Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.

Abstract: The present invention discloses an electrical connector and an electrical connector assembly. The electrical connector includes a circuit board, a connection port, and an insulating member. The circuit board has a conductive region, located on a surface of the circuit board. The connection port is arranged on the surface of the circuit board, and the connection port is electrically connected to the circuit board. The insulating member is arranged on the circuit board, and surrounds an outer periphery of the connection port. The insulating member includes a metal layer, arranged on an outer surface of the insulating member.

Abstract: The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes: a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a magnetic device disposed in the semiconductor chip, a first magnetic field shielding at least partially surrounding the third surface, a second magnetic field shielding, including a top surface facing the second surface of the semiconductor chip, and a molding surrounding the semiconductor chip, wherein the entire top surface of the second magnetic field shielding is in direct contact with the molding.

Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

Abstract: A frequency reconfigurable phased array system comprises a signal generator outputting a power signal with an adjustable frequency, a plurality of radio frequency (RF) modules receiving the power signal, a control module generating excitation mode parameter sets and material processing event sets, a first database storing the excitation mode parameter sets, and a second database storing the material processing event sets. The control module generates a material processing schedule by selecting one of the material processing event sets based on a material recipe, an average power, and a total time of a material, and controls a signal frequency of the signal generator according to the material processing schedule and the excitation mode parameter sets, and a RF phase and a RF power of each of the RF modules, to have the RF modules generating a power signal.

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.

Abstract: A controller of a touch display device is configured to perform steps of: transmitting a main uplink signal to an input device, the main uplink signal indicating an amount of a plurality of downlink signals transmitted in a frame; transmitting a first sub-uplink signal to the input device, the first sub-uplink signal notifying the input device of a time length of a first downlink signal among the plurality of downlink signals; transmitting a second sub-uplink signal to the input device, the second sub-uplink signal notifying the input device of a time length of a second downlink signal among the plurality of downlink signals; and receiving the plurality of downlink signals from the input device.

Abstract: A microwave heating method includes following steps: setting multiple microwave heating modes and their corresponding arrangements of resonator; selecting one of the microwave heating modes according to a heating condition; and, disposing an object to be heated and at least one resonator into a heating chamber, and providing a microwave signal to heat the object to heated, wherein a resonance frequency of the at least one resonator is corresponding to a frequency of the microwave signal, and the at least one resonator is arranged in the arrangement corresponding to the selected microwave heating mode. A microwave heating device suitable for the above microwave heating method is also proposed.

Abstract: A lamination forming system includes a melt extruder, a nozzle head and a carrier unit. The melt extruder is configured to melt a plastic raw material into a plastic melt and to deliver the same. The nozzle head includes a sprue channel that has an inlet connected to the melt extruder for entry of the melt plastic into the sprue channel, and an outlet disposed distally from the inlet to deliver the plastic melt from the sprue channel. The carrier unit includes a slide table controllable to move relative to the nozzle head. The slide table is configure to carry the plastic melt outputted from the nozzle head.

Abstract: A lock assembly includes a casing, a blocking unit, and a lock unit. The blocking unit includes a blocking member operable to move between an open position and a block position. The lock unit includes an engaging member, an electric unlock module, and a manual unlock module. The engaging member has a main body having first and second abutment portions, and is movable between an engaging position for engaging the blocking member when the blocking member is in the block position, and an unlocked position for disengaging from the blocking member. One of the electric unlock module and the manual unlock module is operable to abut a push member thereof against a corresponding one of the first and second abutment portions to linearly move the engaging member.

Abstract: The invention provides a chip structure of a micro light-emitting diode display, comprising a package substrate, at least one light-emitting diode (LED) element, at least one metal oxide semiconductor field effect transistor (MOSFET), and a connection line. The LED element and the MOSFET are positioned on the package substrate, and each MOSFET comprises a source connected with the input voltage in common, a gate connected with a main control circuit, and a drain. An end of the LED element is connected with the drain of the MOSFET through the connection line, and the other end of the LED element is independently connected with a source drive circuit. Therefore, the MOSFET is provided on the package substrate and integrated in a chip structure, so as to achieve a better heat dissipation effect and requirements of high density and brightness.

Abstract: A biodegradable plastic composition is used to manufacture a biodegradable plastic. The biodegradable plastic composition includes a biodegradable polyester, a polysaccharide, and a modifier. The modifier is used to compound the polysaccharide and the biodegradable polyester to obtain a biodegradable plastic. The biodegradable plastic has a tensile strength greater than 3 MPa and an elongation greater than 81%.

Abstract: A suspicious event analysis device includes: a display device; a communication circuit, arranged to operably receive multiple suspicious activities records related to multiple computing devices in a target network and corresponding multiple time stamps and multiple attribute tags through internet; a storage circuit, arranged to operably store a suspicious event sequence diagram generating program; and a control circuit, arranged to operably execute the suspicious event sequence diagram generating program to conduct a suspicious event sequence diagram generating operation, so as to identify multiple suspicious events related to the target network as well as multiple time records corresponding to the multiple suspicious events, and to generate and display a suspicious event sequence diagram corresponding to the multiple suspicious events according to the multiple suspicious events and the multiple time records.

Abstract: A high hardness flexible hard coating film is disclosed. The high hardness flexible hard coating film comprises a substrate film and a hard coating layer. The hard coating layer comprises a (meth)acrylate binder and reactive silica nanoparticles, wherein the reactive silica nanoparticles comprise reactive (meth)acrylate modified silica nanoparticles and reactive (meth)acrylate-polyhedral oligomeric silsesquioxane (POSS) modified silica nanoparticles. The high hardness flexible hard coating film will not crack or fracture under an dynamic inward folding test for performing 180° bend testing at a radius of 1 mm with 2×105 times, and the pencil hardness (JIS K 5400) thereof is 6H or more.

Abstract: A container includes a container body and an air processing system. The container body includes a plurality of walls defining an interior space for receiving wafers. The air processing system is attached to the container body. The air processing system includes an exchange module, an air extraction module, a first contaminant removal module, a processing module, a second contaminant removal module, a controller module and a power module. The exchange module is coupled to one of the walls of the container body. The air extraction module extracts air from the container body. The first contaminant removal module is coupled to the air extraction module and the exchange module. The processing module is coupled to the air extraction module. The second contaminant removal module is coupled to the processing module and the exchange module. The controller module is configured to turn the air extraction module on and off.

Abstract: Examples described herein relate to an analog front-end (AFE). The AFE includes a trans-impedance amplifier to receive an input current and generate a pair of the differential voltage signals based on the input current and a reference current. Further, the AFE includes a dynamic voltage slicer to receive the differential voltage signals at input terminals and supply digital voltages at output terminals. The dynamic voltage slicer includes a preamplifier to generate a pair of intermediate voltages based on the differential voltage signals sampled at a predetermined frequency. The dynamic voltage slicer also includes a voltage latch circuit coupled to the preamplifier, wherein the voltage latch circuit is to regenerate a pair of digital voltages based on the pair of the intermediate voltages. Moreover, the AFE includes a logic latch coupled to the dynamic voltage slicer to provide digital output states based on the pair of the digital voltages.

Abstract: A chip on film package including a chip and a flexible film. The chip includes bumps disposed on the chip and is mounted on the flexible film. The flexible film includes first vias, second vias, upper leads and lower leads. The first vias and the second vias penetrate the flexible film and are arranged on two opposite sides of a reference line respectively. A distance between one of the first vias and one of the second vias, which are closer to a first side of the chip, is longer than that between another one of the first vias and another one of the second, which are further from the first side. The upper leads are disposed on the upper surface connected between the vias and the bumps. The lower leads are disposed on the lower surface and connected to the vias.

Abstract: Examples described herein relate to an analog front-end (AFE). The AFE includes a trans-impedance amplifier to receive an input current and generate a pair of the differential voltage signals based on the input current and a reference current. Further, the AFE includes a dynamic voltage slicer to receive the differential voltage signals at input terminals and supply digital voltages at output terminals. The dynamic voltage slicer includes a preamplifier to generate a pair of intermediate voltages based on the differential voltage signals sampled at a predetermined frequency. The dynamic voltage slicer also includes a voltage latch circuit coupled to the preamplifier, wherein the voltage latch circuit is to regenerate a pair of digital voltages based on the pair of the intermediate voltages. Moreover, the AFE includes a logic latch coupled to the dynamic voltage slicer to provide digital output states based on the pair of the digital voltages.