Abstract: A touch controller and a noise detection method that are capable of accurately detecting noises in a sensing signal are introduced. The touch controller may include a demodulator that is configured to receive a sensing signal and demodulate the sensing signal with a first frequency during a touch detection period. The demodulator may include a first filter that is configured to perform a noise detection operation on the sensing signal to output a first noise detection signal with a second frequency range adjacent to the first frequency. The first filter may have a plurality of peak frequencies different from the first frequency.

Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.

Abstract: A semiconductor device includes a semiconductor layer, a gate electrode disposed on the semiconductor layer, a first dielectric layer disposed on the semiconductor layer and the gate electrode, a source field plate disposed on the semiconductor layer and the first dielectric layer, a second dielectric layer disposed on the source field plate, and a source electrode disposed on the second dielectric layer and electrically connected to the source field plate. The gate electrode has a first sidewall and a second sidewall respectively disposed on the first side and the second side. The source field plate extends from the first side to the second side. A portion of the source field plate is disposed to correspond to the second sidewall. The semiconductor device further includes a third dielectric layer disposed on the source electrode and a drain structure disposed on the second side.

Abstract: A multi-zone gas distribution plate (GDP) for high uniformity in plasma-based etching is provided. A housing defines a process chamber and comprises a gas inlet configured to receive a process gas. A GDP is arranged in the process chamber and is configured to distribute the process gas within the process chamber. The GDP comprises a plurality of holes extending through the GDP, and further comprises a plurality of zones into which the holes are grouped. The zones comprise a first zone and a second zone. Holes of the first zone share a first cross-sectional profile and holes of the second zone share a second cross-sectional profile different than the first cross-sectional profile. A method for designing the multi-zone GDP is also provided.

Abstract: A high hardness flexible hard coating film is disclosed. The high hardness flexible hard coating film comprises a substrate film and a hard coating layer. The hard coating layer comprises a (meth)acrylate binder and reactive silica nanoparticles, wherein the reactive silica nanoparticles comprise reactive (meth)acrylate modified silica nanoparticles and reactive (meth)acrylate-polyhedral oligomeric silsesquioxane (POSS) modified silica nanoparticles. The high hardness flexible hard coating film will not crack or fracture under an dynamic inward folding test for performing 180° bend testing at a radius of 1 mm with 2×105 times, and the pencil hardness (JIS K 5400) thereof is 6H or more.

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory pillar structures extending through the alternating stack. Each of the memory pillar structures includes a respective memory film and a respective vertical semiconductor channel. Dielectric cores contact an inner sidewall of a respective one of the vertical semiconductor channels. A drain-select-level isolation structure laterally extends along a first horizontal direction and contacts straight sidewalls of the dielectric cores at a respective two-dimensional flat interface. The memory pillar structures may be formed on-pitch as a two-dimensional periodic array, and themay drain-select-level isolation structure may cut through upper portions of the memory pillar structures to minimize areas occupied by the drain-select-level isolation structure.

Abstract: A portable electronic device with large display screen-to-body includes a housing, a first display, a circuit board, and an optical module. The first display is a transparent display. The optical module is electrically connected to the circuit board and positioned below the first display. The first display, the optical module, and the circuit board are received in the housing, the optical module is configured to receive external light passing through the first display even as the first display is displaying images. Operating methods for the portable electronic device in various modes are also provided.

Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Abstract: A semiconductor structure includes a substrate, a gate structure disposed on the substrate, a source structure and a drain structure disposed on opposite sides of the gate structure, and a first dielectric layer. The gate structure includes a gate electrode disposed on the substrate and a gate metal layer electrically connected to the gate electrode and serving as a gate field plate. The source structure includes a source electrode disposed on the substrate and a first source metal layer electrically connected to the source electrode and extending in the direction from the gate electrode to the drain structure. The first dielectric layer is disposed on the gate metal layer. The electric potential of the first source metal layer is different from that of the gate metal layer. The first source metal layer exposes at least a portion of the first dielectric layer directly above the gate metal layer.

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

Abstract: A quick release device of a hand tool includes: a main body; an operating portion, including a slidable sleeve movably disposed around the main body and a pin radially inserted into the slidable sleeve, the operating portion further including a movable rod movably disposed in the main body, the pin connected with the movable rod; an annular plastic body, rotatably disposed around the slidable sleeve and corresponding to the pin, a stepped structure formed between the slidable sleeve and the annular plastic body; an identification portion, disposed around the annular plastic body; wherein the slidable sleeve is movable between first and second positions, when the slidable sleeve moves toward the first position, the pin drives the movable rod to move toward a fixing position; when the slidable sleeve moves toward the second position, the pin pushes the movable rod to move toward a releasing position.

Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.

Abstract: In some embodiments, the present disclosure relates to a method, comprising the performing of a reset operation to a resistive random access memory (RRAM) cell. A first voltage bias having a first polarity is applied to the RRAM cell. An absolute value of the first voltage bias is greater than an absolute value of a first reset voltage. The application of the first voltage bias induces the RRAM cell to change from a low resistance to an intermediate resistance greater than the low resistance. A second voltage bias having a second polarity oppose to the first polarity is then applied to the RRAM cell. An absolute value of the second reset voltage is less than an absolute value of the second voltage bias and less than the absolute value of the first reset voltage. The application of the second voltage bias induces the RRAM cell to have a high resistance.

Abstract: The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes: a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a magnetic device disposed in the semiconductor chip, a first magnetic field shielding at least partially surrounding the third surface, a second magnetic field shielding, including a top surface facing the second surface of the semiconductor chip, and a molding surrounding the semiconductor chip, wherein the entire top surface of the second magnetic field shielding is in direct contact with the molding.

Abstract: A protective shell is provided for an electronic device with a built-in antenna. The protective shell includes a plate body, a first penetrating part and an auxiliary grounding element. The first penetrating part is located on the plate body in correspondence with the built-in antenna of the electronic device. The first penetrating part is made of insulating material. The auxiliary grounding element is disposed on the plate body in correspondence with a ground wire of the built-in antenna of the electronic device.