Patents by Inventor Ching-An LIU
Ching-An LIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11823769Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In one aspect, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In one aspect, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.Type: GrantFiled: August 28, 2021Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
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Publication number: 20230368837Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Meng-Sheng Chang, Chia-En HUANG, Yi-Ching LIU, Yih Wang
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Publication number: 20230361100Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.Type: ApplicationFiled: July 5, 2023Publication date: November 9, 2023Inventors: YI-CHING LIU, YIH WANG, CHIA-EN HUANG
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Publication number: 20230345732Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.Type: ApplicationFiled: July 3, 2023Publication date: October 26, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Han-Jong Chia, Yi-Ching Liu, Chia-En Huang, Sheng-Chen Wang, Feng-Cheng Yang, Chung-Te Lin
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Patent number: 11795245Abstract: A hydrophobic polyvinyl alcohol and a method for preparing hydrophobic polyvinyl alcohol are provided. The hydrophobic polyvinyl alcohol includes a first repeat unit represented by Formula (I), a second repeat unit represented by Formula (II), and a third repeat unit represented by Formula (III) wherein R1 is —Si(R2)3, R2 is independently C1-6 alkoxy group, C6-18 alkyl group, or C6-22 alkenyl group, and at least one R2 is C6-18 alkyl group or C6-22 alkenyl group; R3 and R4 are independently C6-18 alkyl group or C6-22 alkenyl group; j is 3 to 7; and k is 1 to 30.Type: GrantFiled: June 22, 2022Date of Patent: October 24, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Chun Liu, Pei-Ching Liu, Ting-Ting Chang, Tien-Shou Shieh
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Publication number: 20230326510Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.Type: ApplicationFiled: June 16, 2023Publication date: October 12, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Peng-Chun Liou, Zhiqiang Wu, Chung-Wei Wu, Yi-Ching Liu, Yih Wang
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Publication number: 20230329009Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.Type: ApplicationFiled: April 7, 2022Publication date: October 12, 2023Applicant: Winbond Electronics Corp.Inventors: Chi-Ching Liu, Chih-Chao Huang, Ming-Che Lin, Frederick Chen, Han-Huei Hsu
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Patent number: 11758734Abstract: A semiconductor device includes a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a first lateral direction. The semiconductor device includes third conductive structures each extending along the first lateral direction. The third conductive structures are disposed across the first and second conductive structures. The semiconductor device includes a first semiconductor channel extending along the vertical direction. The first semiconductor channel is disposed between the third conductive structures and the first conductive structure, and between the third conductive structures and the second conductive structure. The first and second conductive structures each have a first varying width along the first lateral direction, and the first semiconductor channel has a second varying width along a second lateral direction.Type: GrantFiled: August 27, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Chun Liou, Zhiqiang Wu, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin
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Patent number: 11758735Abstract: One aspect of this description relates to a semiconductor device. In some embodiments, the semiconductor device includes a first drain/source structure extending in a first direction, a second drain/source structure extending the first direction and spaced from the first drain/source structure in a second direction perpendicular to the first direction, a third drain/source structure extending in the first direction and spaced from the second drain/source structure in the second direction, a first bit line disposed over the first drain/source structure in the first direction, a common select line that includes a portion disposed over the second drain/source structure in the first direction, a second bit line disposed over the third drain/source structure in the first direction, and a charge storage layer coupled to at least a first sidewall of each of the first drain/source structure, the second drain/source structure, and the third drain/source structure.Type: GrantFiled: February 25, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Han Lin, Chia-En Huang, Yi-Ching Liu
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Patent number: 11758740Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.Type: GrantFiled: April 7, 2021Date of Patent: September 12, 2023Assignee: Winbond Electronics Corp.Inventors: Chang-Tsung Pai, Chiung-Lin Hsu, Yu-Ting Chen, Ming-Che Lin, Chi-Ching Liu
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Patent number: 11756591Abstract: Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.Type: GrantFiled: August 28, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Meng-Sheng Chang, Chia-En Huang, Yi-Ching Liu, Yih Wang
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Publication number: 20230282247Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh Lee, Yi-Ching Liu, Chia-En Huang, Jen-Yuan Chang, Yih Wang
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Patent number: 11749664Abstract: A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.Type: GrantFiled: July 12, 2022Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yi-Ching Liu, Yih Wang, Chia-En Huang
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Patent number: 11744080Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device include a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.Type: GrantFiled: December 15, 2020Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Han-Jong Chia, Yi-Ching Liu, Chia-En Huang, Sheng-Chen Wang, Feng-Cheng Yang, Chung-Te Lin
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Publication number: 20230262986Abstract: A ferroelectric memory device includes a semiconductor structure, a stack structure disposed on the semiconductor structure and including multiple dielectric layers and multiple conductive layers that are alternatingly stacked, and multiple memory arrays extending through the stack structure. Each of the memory arrays includes two spaced-apart memory segments connecting to the stack structure, multiple spaced-apart channel portions each being connected to a corresponding one of the memory segments, and multiple pairs of source/bit lines that are spaced apart from each other. Each of the pairs of the source/bit lines is connected between corresponding two of the channel portions. The ferroelectric memory device further includes multiple carrier structures each being connected to one of the source/bit lines in a corresponding one of the pairs of the source/bit lines, and being separated from the other one of the source/bit lines in the corresponding one of the pairs of the source/bit lines.Type: ApplicationFiled: February 11, 2022Publication date: August 17, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Ling LU, Chia-En HUANG, Ya-Yun CHENG, Yi-Ching LIU, Huan-Sheng WEI, Chung-Wei WU
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Publication number: 20230238303Abstract: A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.Type: ApplicationFiled: January 25, 2022Publication date: July 27, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Han LIN, Chia-En HUANG, Yi-Ching LIU
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Patent number: 11705177Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.Type: GrantFiled: September 9, 2021Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Peng-Chun Liou, Zhiqiang Wu, Chung-Wei Wu, Yi-Ching Liu, Yih Wang
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Publication number: 20230225228Abstract: A resistive random access memory is provided. The resistive random access memory includes a conductive line structure and a memory unit. The conductive line structure is disposed in an array area and a periphery circuit area. The memory unit is disposed on the conductive line structure in the array area. The memory unit includes a lower electrode, a resistive switching layer, and an upper electrode. The lower electrode is disposed on the conductive line structure. The resistive switching layer is disposed on the lower electrode. The upper electrode is disposed on the resistive switching layer. The upper surface of the conductive line structure is in direct contact with the lower electrode.Type: ApplicationFiled: January 7, 2022Publication date: July 13, 2023Inventors: Chi-Ching LIU, Chih-Chao HUANG, Shih-Ning TSAI
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Patent number: 11676641Abstract: A memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.Type: GrantFiled: August 30, 2021Date of Patent: June 13, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chieh Lee, Yi-Ching Liu, Chia-En Huang, Chang Jen-Yuan, Yih Wang
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Publication number: 20230174686Abstract: A hydrophobic polyvinyl alcohol and a method for preparing hydrophobic polyvinyl alcohol are provided. The hydrophobic polyvinyl alcohol includes a first repeat unit represented by Formula (I), a second repeat unit represented by Formula (II), and a third repeat unit represented by Formula (III) wherein R1 is —Si(R2)3, R2 is independently C1-6 alkoxy group, C6-18 alkyl group, or C6-22 alkenyl group, and at least one R2 is C6-18 alkyl group or C6-22 alkenyl group; R3 and R4 are independently C6-18 alkyl group or C6-22 alkenyl group; j is 3 to 7; and k is 1 to 30.Type: ApplicationFiled: June 22, 2022Publication date: June 8, 2023Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yi-Chun LIU, Pei-Ching LIU, Ting-Ting CHANG, Tien-Shou SHIEH