Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.

Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.

Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.

Abstract: A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A semiconductor device including a substrate, a plurality of III-nitride semiconductor layers, a source electrode, a gate electrode, a drain electrode, and a doped layer. The III-nitride semiconductor layers are disposed on the substrate. A two dimensional electron gas (2DEG) channel is formed in the III-nitride semiconductor layers. The source electrode, the gate electrode, and the drain electrode are disposed on the III-nitride semiconductor layers. The gate electrode is located between the source electrode and the drain electrode. The source electrode and the drain electrode are electrically connected to the 2DEG channel. A lateral direction is defined from the source electrode to the drain electrode. The doped layer is disposed between the gate electrode and the III-nitride semiconductor layers. The doped layer includes a plurality of dopants, and a concentration of the dopants varies along the lateral direction.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: The semiconductor device includes a substrate, a first GaN field effect transistor, a second GaN field effect transistor, and a GaN diode. The first GaN field effect transistor is disposed on or above the substrate, and the first GaN field effect transistor is a depletion mode field effect transistor. The second GaN field effect transistor is disposed on or above the substrate, and the second GaN field effect transistor is an enhancement mode field effect transistor. The GaN diode is disposed on or above the substrate. The first GaN field effect transistor, the second GaN field effect transistor, and the GaN diode are disposed on or above a same side of the substrate and electrically connected to each other.

Abstract: A light emitting semiconductor element includes at least two electrically conductive units, at least a light emitting semiconductor die and a light transmitting layer. A groove is located between the two electrically conductive units. The light emitting semiconductor die is cross over the electrically conductive units. The light transmitting layer covers the light emitting semiconductor and partially fills within the groove for linking the electrically conductive units.

Abstract: An illumination apparatus includes a first light-emitting device, a second light-emitting device, and a third light-emitting device. The light emitted from the third light-emitting device is selectively mixed with the light emitted from the first light-emitting device or the second light-emitting device to form a white light having a chromaticity coordinate point substantially located on a Black Body Locus. A color of the light emitted from the third light-emitting device is determined by linear relationships between chromaticity coordinate points corresponding to wavelengths of the lights emitted form the first light-emitting device and the second light-emitting device and corresponding to a color temperature of the white light. A method for generating a white light is also disclosed herein.

Abstract: A light emitting element including an epitaxy layer, at least one first electrode, at least one second electrode, a first bonding pad and a second bonding pad. The epitaxy layer includes in sequence a first semiconductor layer, an active layer and a second semiconductor layer, and the first semiconductor layer has an exposed portion exposed from the second semiconductor layer and the active layer. The first electrode is disposed at the exposed portion. The second electrode is disposed at the second semiconductor layer. The first bonding pad is connected with the first electrode. The second bonding pad is connected with the second electrode. Two light emitting elements with different structures and the light emitting module utilizing the light emitting elements mentioned above are also disclosed.

Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.

Abstract: A semiconductor device including a substrate, a heterojunction body, a passivation layer, a source contact, a drain contact, and a gate contact. The heterojunction body disposed on or above the substrate includes a first semiconductor layer, a mask layer, a regrowth layer, and a second semiconductor layer. The first semiconductor layer is disposed on or above the substrate. The mask layer is disposed on or above a portion of the first semiconductor layer. The regrowth layer disposed on the first semiconductor layer and adjacent to the mask layer includes a main portion and at least one inclined portion. The second semiconductor layer is disposed on the mask layer and the regrowth layer. The passivation layer is disposed on the second semiconductor layer. The gate contact is disposed on the passivation layer, between the source contact and the drain contact, and at least above the inclined portion of the regrowth layer.

Abstract: A light emitting semiconductor element includes at least two electrically conductive units, at least a light emitting semiconductor die and a light transmitting layer. A groove is located between the two electrically conductive units. The light emitting semiconductor die is cross over the electrically conductive units. The light transmitting layer covers the light emitting semiconductor and partially fills within the groove for linking the electrically conductive units.

Abstract: A light emitting semiconductor element includes at least two electrically conductive units, at least a light emitting semiconductor die and a light transmitting layer. A groove is located between the two electrically conductive units. The light emitting semiconductor die is cross over the electrically conductive units. The light transmitting layer covers the light emitting semiconductor and partially fills within the groove for linking the electrically conductive units.

Abstract: An illuminating device includes a substrate, an illuminating element, at least one barricade and at least one cover layer. The illuminating element is disposed on the substrate. The barricade is protruded from a surface of the substrate and disposed around the illuminating element continuously or discontinuously to form a first accommodating area. The cover layer is disposed in the first accommodating area for covering the illuminating element.

Abstract: A semiconductor device including a substrate, a heterojunction body, a passivation layer, a source contact, a drain contact, and a gate contact. The heterojunction body disposed on or above the substrate includes a first semiconductor layer, a mask layer, a regrowth layer, and a second semiconductor layer. The first semiconductor layer is disposed on or above the substrate. The mask layer is disposed on or above a portion of the first semiconductor layer. The regrowth layer disposed on the first semiconductor layer and adjacent to the mask layer includes a main portion and at least one inclined portion. The second semiconductor layer is disposed on the mask layer and the regrowth layer. The passivation layer is disposed on the second semiconductor layer. The gate contact is disposed on the passivation layer, between the source contact and the drain contact, and at least above the inclined portion of the regrowth layer.

Abstract: A light-emitting element includes two electrically conductive layers, a flexible insulating layer, a light-emitting chip and an encapsulating body. A groove is formed between the electrically conductive layers. The flexible insulating layer is disposed within the groove and links the electrically conductive layers. The light-emitting chip is placed on one of the electrically conductive layers or crossing over the flexible insulating layer. The light-emitting chip is electrically connected to the electrically conductive layers and covered by the encapsulating body.

Abstract: The semiconductor device includes a substrate, a first GaN field effect transistor, a second GaN field effect transistor, and a GaN diode. The first GaN field effect transistor is disposed on or above the substrate, and the first GaN field effect transistor is a depletion mode field effect transistor. The second GaN field effect transistor is disposed on or above the substrate, and the second GaN field effect transistor is an enhancement mode field effect transistor. The GaN diode is disposed on or above the substrate. The first GaN field effect transistor, the second GaN field effect transistor, and the GaN diode are disposed on or above a same side of the substrate and electrically connected to each other.