Abstract: A package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die and includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via, and the redistribution layer includes a barrier layer and a conductive layer. The conductive layer of the redistribution layer continuously extends between opposite surfaces of the dielectric layer, and a conductive post of the through via extends from the surface of the dielectric layer towards the first die, and the conductive layer of the redistribution layer is separated from the through substrate via by the barrier layer.

Abstract: A package structure includes first and second dies, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die electrically bonded to the first die includes a through substrate via. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The dielectric layer is disposed on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a first barrier layer and a conductive layer on the first barrier layer. The through substrate via is electrically connected to the redistribution layer, and the conductive layer is in contact with a conductive post of the through via and separated from the through substrate via by the first barrier layer therebetween.

Abstract: The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which forms a silicon spacer on the sidewall of the active layer of a thin film transistor (TFT) by way of anisotropic plasma etching in a single direction. The silicon spacer provides a mechanism for laser recrystallization on the sidewall to prevent the active layer from shrinkage or shelling-off after the laser recrystallization. According to the present invention, large grains can be formed in the channel without additional mask during production. By doing so, the characteristics of the components are enhanced; the uniformity is improved; and, the production cost is lowered. Therefore, this technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistor (LTPS-TFT).

Abstract: A method for fabricating polycrystalline silicon film transistors, which includes a polysilicon spacer capping onto a sidewall of an active layer in the thin film transistors by an isotropic dry etching of the silicon film. This method suppresses the shrinkage of the active layer during recrystallization by the laser. Large grains are formed in the channel after recrystallization utilizing a high-energy continuous wavelength laser or an excimer laser annealing the active layer. This process does not require an additional mask. Uniform arrangement of grain boundaries and large grain sizes promotes uniformity of performance of the device, which is important in the fields of low temperature polycrystalline silicon thin film transistors (LTPS-TFTs).

Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

Abstract: The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which forms a silicon spacer on the sidewall of the active layer of a thin film transistor (TFT) by way of anisotropic plasma etching in a single direction. The silicon spacer provides a mechanism for laser recrystallization on the sidewall to prevent the active layer from shrinkage or shelling-off after the laser recrystallization. According to the present invention, large grains can be formed in the channel without additional mask during production. By doing so, the characteristics of the components are enhanced; the uniformity is improved; and, the production cost is lowered. Therefore, this technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistor (LTPS-TFT).

Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

Abstract: The present invention provides a method for fabrication of polycrystalline silicon thin film transistors, which comprises polysilicon spacer capping onto the sidewall of the active layer in thin film transistors by an isotropic dry etching for silicon film. This method can suppress the shrinkage of the active layer during recrystallization by laser. Large grains can be formed in the channel after recrystallization of high-energy continuous wavelength laser or recrystallization of excimer laser annealing on active layer. This process does not require any additional mask. Uniform arrangement of grain boundaries and large grain sizes can promote device performance uniformity. This technique will play an important role in the fields of low temperature polycrystalline silicon thin film transistors (LTPS-TFTs).

Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

Abstract: The present invention provides an apparatus for liquid phase deposition, comprising: a saturation reaction system, including a mixture trough, at least two supply devices for raw materials, a stirrer device, a filter device, and valve control devices; a steady-flow over-saturation loop reaction system, including an over-saturation reaction trough, at least one liquid level control trough, at least two supply devices for raw materials, a stirrer device, a filter device, and valve control devices; an automatic solution concentration monitoring system, for controlling the reactant concentrations; and a waste liquid recycling system, comprising at least two storage troughs, a recycled waste liquid level sensor, a recycled waste liquid sensor, and valve control devices.

Abstract: A method for liquid phase deposition, including the steps of providing at least two raw materials from at least two supply devices of a saturation reaction system into a mixture trough and stirring until saturation occurs, filtering out unnecessary solid-state particles, and providing saturated and filtered liquid into an over-saturation reaction trough of a steady-flow over-saturation loop reaction system and stopping the saturated and filtered liquid when the over-saturation reaction trough is filled and the saturated and filtered liquid over-flows into a liquid level control trough to a pre-determined level. The method also includes the steps of providing a substrate in the over-saturation reaction trough, providing reactants from at least two supply devices into the over-saturation reaction trough, and depositing a thin film onto the substrate when the saturated liquid becomes over-saturated.

Abstract: The present invention discloses a technique of enhancing adhesion between a passivation layer and a low-K dielectric layer, in which a SiO2 layer as the passivation formed on the low-K dielectric layer is subjected to N2O plasma annealing. This technique is useful in improving the yield of a process for preparing Cu damascene interconnection.

Abstract: The present invention discloses a technique of enhancing adhesion between a passivation layer and a low-K dielectric layer, in which a SiO2 layer as the passivation formed on the low-K dielectric layer is subjected to N2O plasma annealing. This technique is useful in improving the yield of a process for preparing Cu damascene interconnection.

Abstract: The present invention provides an apparatus for liquid phase deposition, comprising: a saturation reaction system, including a mixture trough, at least two supply devices for raw materials, a stirrer device, a filter device, and valve control devices; a steady-flow over-saturation loop reaction system, including an over-saturation reaction trough, at least one liquid level control trough, at least two supply devices for raw materials, a stirrer device, a filter device, and valve control devices; an automatic solution concentration monitoring system, for controlling the reactant concentrations; and a waste liquid recycling system, comprising at least two storage troughs, a recycled waste liquid level sensor, a recycled waste liquid sensor, and valve control devices.

Abstract: The present invention provides a technique to reduce a stress of thick spin-on dielectric layer by forming a sandwich dielectric structure, wherein a first dielectric layer is formed on a substrate by spin coating, a liquid phase deposited (LPD) silica layer is formed the first dielectric layer, and a second dielectric layer is formed on the LPD silica layer by spin coating. The LPD silica layer can be further subjected to a nitrogen plasma treatment to enhance its thermal stability and anti-water penetration ability.

Abstract: The present invention is related to a interconnection structure with Cu interconnects and low-k dielectric, in which a barrier dielectric liner made of a nitrogen-containing liquid-phase-deposition (LPD) fluorosilicate glass (FSG) film is used to replace a barrier metal layer and an oxide liner.

Abstract: A low dielectric constant (k) material, such as methylsilsesquioxane (MSQ), used as an interlevel dielectric is expected to reduce the parasitic capacitance in integrated circuit. However, MSQ film can be easily degraded during resist ashing after the film is etched with the damascene trenches being created. The present invention discloses an innovative sidewall capping technology to solve the degradation issue. Prior to resist ashing, a high-quality, low-k oxide film is selectively deposited onto the sidewalls of MSQ trenches using selective liquid-phase deposition. Experimental results demonstrate that the capping oxide can effectively protect the sidewalls of MSQ trenches from ashing-induced degradation.

Abstract: A method of making a polysilicon thin-film transistor is presented. Device characteristics are improved when a silicon dioxide capping layer is formed by an ion plating method.

Abstract: The present invention relates to a method for forming a polyoxide film on a doped polysilicon layer, which is suitable for use as an inter-polysilicon polyoxide film between a doped polysilicon floating gate and a doped polysilicon control gate. The method includes conducting an electrolytic reaction at a room, temperature such that a polyoxide layer is formed on a doped polysilicon layer acting as an anode. The polyoxide layer is preferably further subjected with a rapid thermal processing to improve its electrical characteristics.

Abstract: A method is capable of providing a semiconductor device with a gate having thereon a thicker silicide or metal layer and further having a lower interconnect resistance. The method is further capable of providing the semiconductor device with a polysilicon gate having a recessed tungsten structure for prevention of short circuit between the gate and the drain or the source. For forming a grooved gate structure, a photo-resist is formed on the polysilicon gate before growing on the entire surface of the silicon substrate a silicon dioxide layer. The silicon dioxide layer and the thin gate oxidation layer on drain/source are etched vertically by a reactive ion etching until the photo-resist and the silicon surface of drain/source are exposed. A plurality of spacers are thus formed on the side walls of the photo-resist/polysilicon gate. Upon stripping the photo-resist, the grooved gate structure is formed on the semiconductor device.