Patents by Inventor Ching-Fa Yeh

Ching-Fa Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5614270
    Abstract: A silicon dioxide layer grown by liquid phase deposition is, subjected to an oxygen or hydrogen plasma treatment to enhance the physical and electrical properties thereof. The plasma treatment is carried out at a temperature of about 300.degree. C.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: March 25, 1997
    Assignee: National Science Council
    Inventors: Ching-Fa Yeh, Shyue S. Lin
  • Patent number: 4961101
    Abstract: In a semiconductor device comprising a plurality of planar high-voltage insulated-gate field-effect transistors in which offset regions are provided in portions of the semiconductor substrate near the junctions of adjacent drain regions and near the substrate surface additional, low impurity concentration offset regions are formed in the semiconductor substrate in such a manner that each low impurity concentration offset region is coupled to a source region and is located between the drain regions of the field-effect transistors adjacent to each other and near the semiconductor surface, whereby reduction of the "on resistance" is achieved without affecting the FET sustaining voltage.
    Type: Grant
    Filed: April 20, 1988
    Date of Patent: October 2, 1990
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Ching Fa Yeh, Yuji Yatsuda
  • Patent number: 4818719
    Abstract: A method of manufacturing a semiconductor device having a high voltage CMOS unit for an ordinary logic operation and a MOS unit which are provided in a single semiconductor substrate of a first conduction type. The method includes the steps of performing an element region making process for making a well of a second conduction type in the substrate, performing a process for providing field-effect transistors having channels of mutually different conduction types in the substrate and the well, and then performing a process for providing electrode wiring layers. Finally, a process is performed for providing a first impurity region having a particular conduction type and serving as a channel stopper of the CMOS unit and a second impurity region having the conduction type of the first impurity region and serving as an offset low-resistance layer of the high voltage MOS unit.
    Type: Grant
    Filed: July 16, 1987
    Date of Patent: April 4, 1989
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Ching-Fa Yeh, Yasunao Misawa, Yuji Yatsuda