Patents by Inventor Ching-Fang Chen
Ching-Fang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11017149Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.Type: GrantFiled: May 11, 2020Date of Patent: May 25, 2021Inventors: Yi-Lin Chuang, Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou, Yun-Han Lee
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Patent number: 11002788Abstract: A circuit test structure including an interposer for electrically connection to a chip, wherein the interposer includes a conductive line, and the conductive line traces a perimeter of the interposer. The circuit test structure further includes at least three electrical connections to the conductive line. The circuit test structure further includes a testing site. The circuit test structure further includes a through substrate via (TSV) connecting the testing site to the conductive line.Type: GrantFiled: May 2, 2019Date of Patent: May 11, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fang Chen, Hsiang-Tai Lu, Chih-Hsien Lin
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Publication number: 20210089630Abstract: A method, includes: extracting a design data using a computer, wherein the design data includes a net name and a connective layer name of each layout design in each cell; generating a layout pattern corresponding to the design data by assigning an ID to said each layout design, wherein the ID includes a first indicator indicative of the net name and a second indicator indicative of the connective layer name; and checking the layout pattern to locate an error of the layout pattern.Type: ApplicationFiled: September 25, 2019Publication date: March 25, 2021Inventors: CHIA CHENG CHEN, CHING-FANG CHEN, HUANG-YU CHEN, JEN PING HSU
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Publication number: 20200379013Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.Type: ApplicationFiled: August 18, 2020Publication date: December 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
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Patent number: 10782318Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.Type: GrantFiled: October 20, 2017Date of Patent: September 22, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
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Publication number: 20200272777Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Wei-Li CHEN, Wei-Pin CHANGCHIEN, Yung-Chin HOU, Yun-Han LEE
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Publication number: 20200185324Abstract: A system (including a processor and memory with computer program code) that is configured to execute a method which includes generating the layout diagram including: selecting a circuit cell which includes an active element; bundling, for purposes of placement, the circuit cell and an inter-layer via together as an integral unit; placing the integral unit of the circuit cell and the inter-layer via in a first device layer of the layout diagram; and placing a metal pattern in a second device layer of the layout diagram; and wherein the placing the integral unit of the circuit cell and the inter-layer via forms a direct electrical connection channel between the circuit cell and the metal pattern.Type: ApplicationFiled: February 14, 2020Publication date: June 11, 2020Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Jia-Jye SHEN
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Patent number: 10678973Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.Type: GrantFiled: October 4, 2017Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Ching-Fang Chen, Wei-Li Chen, Wei-Pin Changchien, Yung-Chin Hou, Yun-Han Lee
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Patent number: 10566278Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. Such a method includes: placing a power supply rail pattern in a first device layer of the IC; bundling, for purposes of placement, a voltage level shifter and one or more inter-layer vias together as an integral unit; and placing the integral unit in the first device layer of the IC design such that one or more metal line patterns in the voltage level shifter are located parallel to albeit without overlapping the power supply rail pattern. The placing the integral unit forms a direct electrical connection channel between the voltage level shifter and a metal pattern in a second device layer of the IC design. At least one of the placing operations is performed using a layout generating machine.Type: GrantFiled: June 12, 2017Date of Patent: February 18, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
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Publication number: 20190257880Abstract: A circuit test structure including an interposer for electrically connection to a chip, wherein the interposer includes a conductive line, and the conductive line traces a perimeter of the interposer. The circuit test structure further includes at least three electrical connections to the conductive line. The circuit test structure further includes a testing site. The circuit test structure further includes a through substrate via (TSV) connecting the testing site to the conductive line.Type: ApplicationFiled: May 2, 2019Publication date: August 22, 2019Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
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Patent number: 10288676Abstract: A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site. The Kelvin test structure is configured to electrically connect the testing site to the conductive line.Type: GrantFiled: June 26, 2017Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fang Chen, Hsiang-Tai Lu, Chih-Hsien Lin
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Publication number: 20180326617Abstract: A diamond wire saw includes a steel wire, a molded sleeve, and a plurality of diamond bead bearing units. The molded sleeve surrounds and is bonded to the steel wire. The diamond bead bearing units are disposed around and bonded to the molded sleeve. Each of the diamond bead bearing units includes a tubular body and a functional layer that covers the tubular body and that contains a plurality of abrasive diamond particles. The molded sleeve is made of polyether-type thermoplastic polyurethane, and has a Shore hardness of greater than or equal to 70 D.Type: ApplicationFiled: May 12, 2017Publication date: November 15, 2018Applicant: STONE & RESOURCE INDUSTRY R&D CENTERInventors: Chih-Chen KUO, Ching-Fang CHEN, Bo-Hong WU, Chao-Hung LEE, Bo-Hua CHENG
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Publication number: 20180268096Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.Type: ApplicationFiled: October 4, 2017Publication date: September 20, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Wei-Li CHEN, Wei-Pin CHANGCHIEN, Yung-Chin HOU, Yun-Han LEE
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Patent number: 9952279Abstract: A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.Type: GrantFiled: December 21, 2012Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang, Chung-Sheng Yuan, Ching-Fang Chen, Wen-Wen Hsieh, Meng-Lin Chung
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Publication number: 20180038894Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.Type: ApplicationFiled: October 20, 2017Publication date: February 8, 2018Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
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Patent number: 9817029Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.Type: GrantFiled: December 7, 2011Date of Patent: November 14, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
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Publication number: 20170292991Abstract: A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site. The Kelvin test structure is configured to electrically connect the testing site to the conductive line.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
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Publication number: 20170278789Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. Such a method includes: placing a power supply rail pattern in a first device layer of the IC; bundling, for purposes of placement, a voltage level shifter and one or more inter-layer vias together as an integral unit; and placing the integral unit in the first device layer of the IC design such that one or more metal line patterns in the voltage level shifter are located parallel to albeit without overlapping the power supply rail pattern. The placing the integral unit forms a direct electrical connection channel between the voltage level shifter and a metal pattern in a second device layer of the IC design. At least one of the placing operations is performed using a layout generating machine.Type: ApplicationFiled: June 12, 2017Publication date: September 28, 2017Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Jia-Jye SHEN
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Patent number: 9689914Abstract: A method of testing a three-dimensional integrated circuit (3DIC) includes applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer substantially parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors. The method further includes measuring a current responsive to the applied voltage. The method further includes determining an integrity of the 3DIC based on the measured current.Type: GrantFiled: April 30, 2015Date of Patent: June 27, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fang Chen, Hsiang-Tai Lu, Chih-Hsien Lin
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Patent number: 9679840Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.Type: GrantFiled: March 20, 2014Date of Patent: June 13, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen