Patents by Inventor Ching-Fang Chen
Ching-Fang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9679840Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.Type: GrantFiled: March 20, 2014Date of Patent: June 13, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin Chuang, Ching-Fang Chen, Jia-Jye Shen
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Patent number: 9613174Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.Type: GrantFiled: April 6, 2015Date of Patent: April 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
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Publication number: 20150270214Abstract: A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. The layout method can include placing a circuit cell and an inter-layer via together in a first device layer of the IC structure, and placing a metal pattern in a second device layer of the IC structure. The inter-layer via and the metal pattern may be configured to form a direct connection channel for the circuit cell and the metal pattern.Type: ApplicationFiled: March 20, 2014Publication date: September 24, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin CHUANG, Ching-Fang CHEN, Jia-Jye SHEN
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Publication number: 20150234004Abstract: A method of testing a three-dimensional integrated circuit (3DIC) includes applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer substantially parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors. The method further includes measuring a current responsive to the applied voltage. The method further includes determining an integrity of the 3DIC based on the measured current.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
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Publication number: 20150213182Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.Type: ApplicationFiled: April 6, 2015Publication date: July 30, 2015Inventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
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Patent number: 9040986Abstract: A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors.Type: GrantFiled: January 23, 2012Date of Patent: May 26, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fang Chen, Hsiang-Tai Lu, Chih-Hsien Lin
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Patent number: 9003338Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.Type: GrantFiled: March 15, 2013Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
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Patent number: 8984728Abstract: A drawing device of the present invention includes a first driving element, a bolt, a plurality of second driving elements, and a plurality of clipping rods. The first driving element drives the second driving elements to rotate simultaneously, so that the clipping rods are able to be rotated and operated. Also, a hook portion of each clipping rod is able to hook to a bottom of objects to be drawn out, and the bolt is disposed on a threaded hole of the first driving element and abuts against the objects to be drawn out. At the same time, the clipping rods are moved outward.Type: GrantFiled: May 10, 2012Date of Patent: March 24, 2015Assignee: Shine Yen Industrial Co., Ltd.Inventors: Lung-Shan Chen, Lien-Chin Chen, Ching-Fang Chen
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Patent number: 8863062Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.Type: GrantFiled: July 9, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee
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Publication number: 20140282305Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: William Wu Shen, Yun-Han Lee, Chin-Chou Liu, Hsien-Hsin Lee, Chung-Sheng Yuan, Chao-Yang Yeh, Wei-Cheng Wu, Ching-Fang Chen
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Patent number: 8707238Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.Type: GrantFiled: May 31, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee, Charles C. C. Liu
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Publication number: 20130326463Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee, Charles C.C. Liu
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Publication number: 20130290914Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.Type: ApplicationFiled: July 9, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee
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Publication number: 20130187156Abstract: A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors.Type: ApplicationFiled: January 23, 2012Publication date: July 25, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Fang CHEN, Hsiang-Tai LU, Chih-Hsien LIN
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Patent number: 8490518Abstract: According to the present invention, the oil filter replacement device has a number of pins for clamping an oil filter, and the pins are extended eccentrically from corresponding secondary gear members. The secondary gear members are engaged to spin simultaneously by a main gear member. As such, the pins could be adjusted to fit on oil filters of various sizes. Additionally, each pin is rotatable and has at least a flat face. As the pins rolls along the circumference of the oil filter, their flat faces are turned to interface the flat faces around the oil filter. As such, the oil filter is tightly and reliably clamped by the oil filter replacement device, thereby preventing the problem of uneven exertion of force and deforming the oil filter.Type: GrantFiled: March 3, 2011Date of Patent: July 23, 2013Assignee: Shine Yen Industrial Co., Ltd.Inventors: Lung-Shan Chen, Lien-Chin Chen, Ching-Fang Chen
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Publication number: 20130147505Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer WANG, Ching-Fang CHEN, Sandeep Kumar GOEL, Chung-Sheng YUAN, Chao-Yang YEH, Chin-Chou LIU, Yun-Han LEE, Hung-Chih LIN
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Publication number: 20120284982Abstract: A drawing device of the present invention includes a first driving element, a bolt, a plurality of second driving elements, and a plurality of clipping rods. The first driving element drives the second driving elements to rotate simultaneously, so that the clipping rods are able to be rotated and operated. Also, a hook portion of each clipping rod is able to hook to a bottom of objects to be drawn out, and the bolt is disposed on a threaded hole of the first driving element and abuts against the objects to be drawn out. At the same time, the clipping rods are moved outward.Type: ApplicationFiled: May 10, 2012Publication date: November 15, 2012Inventors: Lung-Shan CHEN, Lien-Chin Chen, Ching-Fang Chen
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Publication number: 20120222522Abstract: According to the present invention, the oil filter replacement device has a number of pins for clamping an oil filter, and the pins are extended eccentrically from corresponding secondary gear members. The secondary gear members are engaged to spin simultaneously by a main gear member. As such, the pins could be adjusted to fit on oil filters of various sizes. Additionally, each pin is rotatable and has at least a flat face. As the pins rolls along the circumference of the oil filter, their flat faces are turned to interface the flat faces around the oil filter. As such, the oil filter is tightly and reliably clamped by the oil filter replacement device, thereby preventing the problem of uneven exertion of force and deforming the oil filter.Type: ApplicationFiled: March 3, 2011Publication date: September 6, 2012Inventors: Lung-Shan Chen, Lien-chin Chen, Ching-Fang Chen
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Publication number: 20120079919Abstract: An oil filter canister adapter of the present invention mainly includes a base, a rotatable plate, three rotatable members, and three holders. The rotatable plate and the rotatable members are respectively disposed on the base. The rotatable members contact with the rotatable plate respectively, so that the rotatable plate can rotate and drive the rotatable members to rotate. The holders are detachably disposed on the rotatable members respectively. Distances between any two adjacent holders are consistent in value. The distances between the holders are adjustable when the rotatable members rotate. Therefore, the holders can be detached from the rotatable members. Volume of the adapter is minimized for storage. As such, cost of transportation or storage of the adapter can be well controlled.Type: ApplicationFiled: August 12, 2011Publication date: April 5, 2012Inventors: Lung-Shan Chen, Lien-Chin Chen, Ching-Fang Chen