Abstract: An extreme ultraviolet (EUV) mask and method of forming an EUV mask are provided. The method includes forming a mask layer on a semiconductor wafer, generating extreme ultraviolet (EUV) light by a lithography exposure system, forming patterned EUV light by patterning the EUV light by a mask including an absorber having extinction coefficient at an EUV wavelength that exceeds extinction coefficients of TaBN and TaN at the EUV wavelength, and exposing the mask layer by the patterned EUV light.

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

Abstract: A method includes: generating a designed mask overlay mark associated with an actual mask overlay mark to be formed in a mask; forming the actual mask overlay mark in the mask based on the designed mask overlay mark, the actual mask overlay mark including a plurality of overlay patterns; forming a device feature pattern adjacent to the actual mask overlay mark; forming an alignment of the mask by a mask metrology apparatus including a light source having a wavelength and a numerical aperture, wherein a pitch between adjacent two of the plurality of overlay patterns does not exceed the wavelength divided by twice the numerical aperture; and forming a pattern in a layer of a wafer by transferring the device feature pattern while the mask is under the alignment.

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

Abstract: An extreme ultraviolet (EUV) mask, includes a substrate, a reflective multilayer stack on the substrate, and a single layer or multi-layer capping feature on the reflective multilayer stack. The capping feature includes a capping layer or capping layers including a material having an amorphous structure. Other described embodiments include capping layer(s) that contain element(s) having a first solid carbon solubility less than about 3. In multilayer capping feature embodiments, element(s) of the respective capping layers have different solid carbon solubility properties.

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

Abstract: A probe head includes a probe seat, a first spring probe penetrating through upper, middle and lower dies of the probe seat for transmitting a first test signal, and at least two shorter second spring probes penetrating through the lower die for transmitting a second test signal with higher frequency. Two second spring probes are electrically connected in a way that top ends thereof are abutted against two electrically conductive contacts on a bottom surface of the middle die electrically connected by a connecting circuit therein. The lower die has a communicating space and at least two lower installation holes communicating therewith and each accommodating a second spring probe partially located in the communicating space. The probe head is adapted for concurrent high and medium or low frequency signal tests, meets fine pitch and high frequency testing requirements and prevents probe cards from too complicated circuit design.

Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

Abstract: A probe head includes a probe seat, a first spring probe penetrating through upper, middle and lower dies of the probe seat for transmitting a first test signal, and at least two shorter second spring probes penetrating through the lower die for transmitting a second test signal with higher frequency. Two second spring probes are electrically connected in a way that top ends thereof are abutted against two electrically conductive contacts on a bottom surface of the middle die electrically connected by a connecting circuit therein. The lower die has a communicating space and at least two lower installation holes communicating therewith and each accommodating a second spring probe partially located in the communicating space. The probe head is adapted for concurrent high and medium or low frequency signal tests, meets fine pitch and high frequency testing requirements and prevents probe cards from too complicated circuit design.

Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.

Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.

Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.

Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.

Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.

Abstract: An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.