Patents by Inventor Ching-Fang Yu

Ching-Fang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955026
    Abstract: A method, computer program product, and computer system for public speaking guidance is provided. A processor retrieves speaker data regarding a speech made by a user. A processor separates the speaker data into one or more speaker modalities. A processor extracts one or more speaker features from the speaker data for the one or more speaker modalities. A processor generates a performance classification based on the one or more speaker features. A processor sends to the user guidance regarding the speech based on the performance classification.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 9, 2024
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Fang Lin, Ching-Chun Liu, Ting-Chieh Yu, Yu-Siang Chen, Ryan Young
  • Publication number: 20230375911
    Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Inventors: Ping-Hsun LIN, Pei-Cheng HSU, Ching-Fang YU, Ta-Cheng LIEN, Chia-Jen CHEN, Hsin-Chang LEE
  • Patent number: 11815804
    Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: November 14, 2023
    Inventors: Ping-Hsun Lin, Pei-Cheng Hsu, Ching-Fang Yu, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
  • Publication number: 20230161241
    Abstract: An extreme ultraviolet (EUV) mask, includes a substrate, a reflective multilayer stack on the substrate, and a single layer or multi-layer capping feature on the reflective multilayer stack. The capping feature includes a capping layer or capping layers including a material having an amorphous structure. Other described embodiments include capping layer(s) that contain element(s) having a first solid carbon solubility less than about 3. In multilayer capping feature embodiments, element(s) of the respective capping layers have different solid carbon solubility properties.
    Type: Application
    Filed: May 19, 2022
    Publication date: May 25, 2023
    Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Wei-Hao LEE, Ping-Hsun LIN, Ta-Cheng LIEN, Ching-Fang YU
  • Publication number: 20220342292
    Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.
    Type: Application
    Filed: September 22, 2021
    Publication date: October 27, 2022
    Inventors: Ping-Hsun LIN, Pei-Cheng HSU, Ching-Fang YU, Ta-Cheng LIEN, Chia-Jen CHEN, Hsin-Chang LEE
  • Patent number: 11150269
    Abstract: A probe head includes a probe seat, a first spring probe penetrating through upper, middle and lower dies of the probe seat for transmitting a first test signal, and at least two shorter second spring probes penetrating through the lower die for transmitting a second test signal with higher frequency. Two second spring probes are electrically connected in a way that top ends thereof are abutted against two electrically conductive contacts on a bottom surface of the middle die electrically connected by a connecting circuit therein. The lower die has a communicating space and at least two lower installation holes communicating therewith and each accommodating a second spring probe partially located in the communicating space. The probe head is adapted for concurrent high and medium or low frequency signal tests, meets fine pitch and high frequency testing requirements and prevents probe cards from too complicated circuit design.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: October 19, 2021
    Assignee: MPI CORPORATION
    Inventors: Hui-Pin Yang, Shang-Jung Hsieh, Yu-Wen Chou, Ching-Fang Yu, Huo-Kang Hsu, Chin-Tien Yang
  • Publication number: 20210208505
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Application
    Filed: March 19, 2021
    Publication date: July 8, 2021
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Patent number: 10955746
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Publication number: 20210048452
    Abstract: A probe head includes a probe seat, a first spring probe penetrating through upper, middle and lower dies of the probe seat for transmitting a first test signal, and at least two shorter second spring probes penetrating through the lower die for transmitting a second test signal with higher frequency. Two second spring probes are electrically connected in a way that top ends thereof are abutted against two electrically conductive contacts on a bottom surface of the middle die electrically connected by a connecting circuit therein. The lower die has a communicating space and at least two lower installation holes communicating therewith and each accommodating a second spring probe partially located in the communicating space. The probe head is adapted for concurrent high and medium or low frequency signal tests, meets fine pitch and high frequency testing requirements and prevents probe cards from too complicated circuit design.
    Type: Application
    Filed: August 11, 2020
    Publication date: February 18, 2021
    Applicant: MPI CORPORATION
    Inventors: Hui-Pin YANG, Shang-Jung HSIEH, Yu-Wen CHOU, Ching-Fang YU, Huo-Kang HSU, Chin-Tien YANG
  • Patent number: 10691017
    Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Publication number: 20190072849
    Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.
    Type: Application
    Filed: November 6, 2018
    Publication date: March 7, 2019
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Publication number: 20190033720
    Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.
    Type: Application
    Filed: January 3, 2018
    Publication date: January 31, 2019
    Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
  • Patent number: 10126644
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Patent number: 9933699
    Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Sheng-Chi Chin, Ting-Hao Hsu, Mark Chang
  • Publication number: 20170227843
    Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.
    Type: Application
    Filed: February 9, 2016
    Publication date: August 10, 2017
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
  • Patent number: 9548209
    Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Chia-Ching Huang, Ting-Hao Hsu
  • Publication number: 20160274471
    Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Sheng-Chi Chin, Ting-Hao Hsu, Mark Chang
  • Patent number: 9354510
    Abstract: An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 9305346
    Abstract: A method of inspecting fabricated articles includes receiving a fabricated article to be inspected for defects, the fabricated article having a pattern thereon, and the pattern being based on a pattern design and creating a rule set for defining critical regions of the pattern as represented in the pattern design, the critical regions being regions in which defects are more likely to be found during inspection. The method also includes applying the rule set to the pattern design to identify a critical region of the pattern on the fabricated article and a non-critical region of the pattern on the fabricated article. Further, the method includes inspecting the non-critical region of the pattern on the fabricated article for defects at first resolution and inspecting the critical region of the pattern on the fabricated article for defects at a second resolution higher than the first resolution.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Ting-Hao Hsu
  • Patent number: 9152035
    Abstract: A lithographic process will use a mask or photomask. The photomask includes a first material layer, the first material layer providing a first outer surface of the photomask. The photomask also includes a second material layer over the first material layer, the second material layer providing a second outer surface of the photomask. The two outer surfaces are substantially in parallel and a distance between the two outer surfaces along a first axis perpendicular to the two outer surfaces defines a thickness of the photomask. Also, the two outer surfaces are connected by a plurality of sides, at least one of the sides is not perpendicular to the two outer surfaces and the at least one of the sides provides substantial area for holding the lithographic photomask.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Yu, Ting-Hao Hsu, Sheng-Chi Chin