Patents by Inventor Ching-Fang Yu
Ching-Fang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955026Abstract: A method, computer program product, and computer system for public speaking guidance is provided. A processor retrieves speaker data regarding a speech made by a user. A processor separates the speaker data into one or more speaker modalities. A processor extracts one or more speaker features from the speaker data for the one or more speaker modalities. A processor generates a performance classification based on the one or more speaker features. A processor sends to the user guidance regarding the speech based on the performance classification.Type: GrantFiled: September 26, 2019Date of Patent: April 9, 2024Assignee: International Business Machines CorporationInventors: Cheng-Fang Lin, Ching-Chun Liu, Ting-Chieh Yu, Yu-Siang Chen, Ryan Young
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Publication number: 20230375911Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.Type: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Inventors: Ping-Hsun LIN, Pei-Cheng HSU, Ching-Fang YU, Ta-Cheng LIEN, Chia-Jen CHEN, Hsin-Chang LEE
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Patent number: 11815804Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.Type: GrantFiled: September 22, 2021Date of Patent: November 14, 2023Inventors: Ping-Hsun Lin, Pei-Cheng Hsu, Ching-Fang Yu, Ta-Cheng Lien, Chia-Jen Chen, Hsin-Chang Lee
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Publication number: 20230161241Abstract: An extreme ultraviolet (EUV) mask, includes a substrate, a reflective multilayer stack on the substrate, and a single layer or multi-layer capping feature on the reflective multilayer stack. The capping feature includes a capping layer or capping layers including a material having an amorphous structure. Other described embodiments include capping layer(s) that contain element(s) having a first solid carbon solubility less than about 3. In multilayer capping feature embodiments, element(s) of the respective capping layers have different solid carbon solubility properties.Type: ApplicationFiled: May 19, 2022Publication date: May 25, 2023Inventors: Hsin-Chang LEE, Pei-Cheng HSU, Wei-Hao LEE, Ping-Hsun LIN, Ta-Cheng LIEN, Ching-Fang YU
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Publication number: 20220342292Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.Type: ApplicationFiled: September 22, 2021Publication date: October 27, 2022Inventors: Ping-Hsun LIN, Pei-Cheng HSU, Ching-Fang YU, Ta-Cheng LIEN, Chia-Jen CHEN, Hsin-Chang LEE
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Patent number: 11150269Abstract: A probe head includes a probe seat, a first spring probe penetrating through upper, middle and lower dies of the probe seat for transmitting a first test signal, and at least two shorter second spring probes penetrating through the lower die for transmitting a second test signal with higher frequency. Two second spring probes are electrically connected in a way that top ends thereof are abutted against two electrically conductive contacts on a bottom surface of the middle die electrically connected by a connecting circuit therein. The lower die has a communicating space and at least two lower installation holes communicating therewith and each accommodating a second spring probe partially located in the communicating space. The probe head is adapted for concurrent high and medium or low frequency signal tests, meets fine pitch and high frequency testing requirements and prevents probe cards from too complicated circuit design.Type: GrantFiled: August 11, 2020Date of Patent: October 19, 2021Assignee: MPI CORPORATIONInventors: Hui-Pin Yang, Shang-Jung Hsieh, Yu-Wen Chou, Ching-Fang Yu, Huo-Kang Hsu, Chin-Tien Yang
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Publication number: 20210208505Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.Type: ApplicationFiled: March 19, 2021Publication date: July 8, 2021Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
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Patent number: 10955746Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.Type: GrantFiled: January 3, 2018Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
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Publication number: 20210048452Abstract: A probe head includes a probe seat, a first spring probe penetrating through upper, middle and lower dies of the probe seat for transmitting a first test signal, and at least two shorter second spring probes penetrating through the lower die for transmitting a second test signal with higher frequency. Two second spring probes are electrically connected in a way that top ends thereof are abutted against two electrically conductive contacts on a bottom surface of the middle die electrically connected by a connecting circuit therein. The lower die has a communicating space and at least two lower installation holes communicating therewith and each accommodating a second spring probe partially located in the communicating space. The probe head is adapted for concurrent high and medium or low frequency signal tests, meets fine pitch and high frequency testing requirements and prevents probe cards from too complicated circuit design.Type: ApplicationFiled: August 11, 2020Publication date: February 18, 2021Applicant: MPI CORPORATIONInventors: Hui-Pin YANG, Shang-Jung HSIEH, Yu-Wen CHOU, Ching-Fang YU, Huo-Kang HSU, Chin-Tien YANG
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Patent number: 10691017Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.Type: GrantFiled: November 6, 2018Date of Patent: June 23, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
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Publication number: 20190072849Abstract: Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.Type: ApplicationFiled: November 6, 2018Publication date: March 7, 2019Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
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Publication number: 20190033720Abstract: An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.Type: ApplicationFiled: January 3, 2018Publication date: January 31, 2019Inventors: Shinn-Sheng Yu, Ching-Fang Yu, Wen-Chuan Wang, Ting-Hao Hsu, Sheng-Chi Chin, Anthony Yen
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Patent number: 10126644Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.Type: GrantFiled: February 9, 2016Date of Patent: November 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
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Patent number: 9933699Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.Type: GrantFiled: March 16, 2015Date of Patent: April 3, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Sheng-Chi Chin, Ting-Hao Hsu, Mark Chang
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Publication number: 20170227843Abstract: The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.Type: ApplicationFiled: February 9, 2016Publication date: August 10, 2017Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Ting-Hao Hsu, Ching-Hsiang Chang, Sheng-Chi Chin
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Patent number: 9548209Abstract: Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.Type: GrantFiled: February 18, 2015Date of Patent: January 17, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Fang Yu, Chia-Ching Huang, Ting-Hao Hsu
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Publication number: 20160274471Abstract: A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventors: Yu-Ching Lee, Ching-Fang Yu, Chun-Hung Lin, Sheng-Chi Chin, Ting-Hao Hsu, Mark Chang
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Patent number: 9354510Abstract: An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.Type: GrantFiled: April 4, 2014Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Fang Yu, Ting-Hao Hsu, Sheng-Chi Chin
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Patent number: 9305346Abstract: A method of inspecting fabricated articles includes receiving a fabricated article to be inspected for defects, the fabricated article having a pattern thereon, and the pattern being based on a pattern design and creating a rule set for defining critical regions of the pattern as represented in the pattern design, the critical regions being regions in which defects are more likely to be found during inspection. The method also includes applying the rule set to the pattern design to identify a critical region of the pattern on the fabricated article and a non-critical region of the pattern on the fabricated article. Further, the method includes inspecting the non-critical region of the pattern on the fabricated article for defects at first resolution and inspecting the critical region of the pattern on the fabricated article for defects at a second resolution higher than the first resolution.Type: GrantFiled: May 31, 2012Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Fang Yu, Ting-Hao Hsu
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Patent number: 9152035Abstract: A lithographic process will use a mask or photomask. The photomask includes a first material layer, the first material layer providing a first outer surface of the photomask. The photomask also includes a second material layer over the first material layer, the second material layer providing a second outer surface of the photomask. The two outer surfaces are substantially in parallel and a distance between the two outer surfaces along a first axis perpendicular to the two outer surfaces defines a thickness of the photomask. Also, the two outer surfaces are connected by a plurality of sides, at least one of the sides is not perpendicular to the two outer surfaces and the at least one of the sides provides substantial area for holding the lithographic photomask.Type: GrantFiled: October 11, 2013Date of Patent: October 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Fang Yu, Ting-Hao Hsu, Sheng-Chi Chin