Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

Abstract: Methods and apparatus for an interposer with a dam used in packaging dies are disclosed. An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: A method comprises attaching a semiconductor die on a first side of a wafer, attaching a first top package on the first side of the wafer and attaching a second top package on the first side of the wafer. The method further comprises depositing an encapsulation layer over the first side of the wafer, wherein the first top package and the second top package are embedded in the encapsulation layer, applying a thinning process to a second side of the wafer, sawing the wafer into a plurality of chip packages and attaching the chip package to a substrate.

Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.

Abstract: A new kind of Sn—In based Pb-free solders with Zn addition is disclosed, which includes: 15˜25 wt % In; 0.05˜1.5 wt % Zn; and balance Sn. When the solder of the present invention is used in the assembly of electrical products, the dissolution rates of the substrates and the growth of the intermetallic compounds formed at the interfaces can be reduced; and thereby the properties of joints can be improved.

Abstract: This invention forms an indium or indium alloy layer on top of a Sn based lead-free solder. The indium or indium alloy layer can be formed by various methods, such as plating, deposition, printing, dipping, etc. The indium-containing layer melts during the soldering process, wets the substrate, and forms a sound solder joint. Since the melting point of indium is 156.6° C., even lower than that of the eutectic Sn—Pb which is at 183° C., so the soldering process can be carried out at a temperature lower than the conventional soldering process. During the soldering process, the indium reacts with the Sn based Pb-free solder alloy. Since the eutectic temperature of Sn—In is at 120° C., during the short time of the soldering process, the surface of the In deposited Pb-free solder remains as the liquid phase and have a good wetting with the substrate, while a In gradient is formed in the In deposited Pb-free solder.

Abstract: A power converter with synchronous rectifying through the control of a current transformer is disclosed. The basic architecture of the power converter includes a flyback transformer (10), a switch controller (20) and a current transformer (30). The secondary winding of the flyback transformer (10) is connected to the primary winding of the current transformer (30) used to control the switch controller (20). The primary winding of the current transformer (30) is connected to a synchronous rectifying switch (Q7). If a current change occurs on the secondary winding of the flyback transformer (10), the current transformer (30) detects the phase change and enables the switch controller (20) to switch off the synchronous rectifying switch (Q7). The current transformer (30) turns off the synchronous rectifying switch (Q7) anticipatorily in the continuous current output mode to prevent any power loss from crossovers.