Abstract: An opportunistic time-borrowing domino logic includes a domino pipeline having a plurality of logic gates coupled in series and controlled by first, second, third and fourth clock signals. The first domino gate in a half-cycle is clocked by either the first or the second clock signals, wherein the last domino gate in a half-cycle is clocked by either the third or the fourth clock cycles. The second clock signal is an inverse of the first clock signal, and the third and fourth clock signals have local delayed clock phases in which the falling edges of the third and fourth clock signals are delayed relative to the falling edges of the respective first and second clock signals. In a first half-cycle, a first type of domino gate is controlled by the first clock signal, with subsequent domino gates of the same type being controlled by the third clock signal.

Abstract: A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is generated and checked to verify data and tag integrity. The parity field is stored in a status array physically separate from the tag array. The status array is offset in timing so that it lags behind the tag array for both read and write operations. Therefore, fields in the status array can be written in the early part of the next clock cycle without affecting the tag array or another operation that may be scheduled for the next time cycle.

Abstract: A set select circuit and method for selecting a set in a set associative cache in a microprocessor. The set select circuit, responsive to a main clock, includes an input latch coupled to receive select data before the main clock cycle. The input latch is transparent to set select data so that predecoding can begin before the main clock. The input latch latches the set select data on the initial clock edge and holds the set select data during the first half of the main clock cycle. A pre-decoder is coupled to the input latch for receiving and predecoding the set select data, and a decoder is coupled to the predecoder for receiving and decoding the pre-decoded set select data to supply an output to an output latch. The output latch is also coupled to a clock inverter to receive the inverted delayed clock signal. The output latch is transparent during the second half of an inverted delayed clock cycle.