Patents by Inventor Ching-Hua Hsieh

Ching-Hua Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240404954
    Abstract: A package and a method of manufacturing the same are provided. The package includes a first die, a second die, a third die, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The third die is disposed on the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the third die and fills in a gap between the first die, the second die, and the third die. The RDL structure is disposed on the third die and the encapsulant.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsai-Tsung Tsai, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Hsiang Chiu, Yi-Da Tsai
  • Publication number: 20240404932
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least includes a redistribution layer, a semiconductor die, an interlink block, and a molding compound. The semiconductor die is disposed on the redistribution layer, and the interlink block is disposed on the redistribution layer and beside the semiconductor die. The interlink block includes an insulating encapsulant and through insulator vias penetrating through the insulating encapsulant. The molding compound disposed on the redistribution layer laterally wraps around the semiconductor die and the interlink block. The interlink block is spaced apart from the semiconductor die with the molding compound there-between. The through insulator vias are isolated from the molding compound by the insulating encapsulant.
    Type: Application
    Filed: May 29, 2023
    Publication date: December 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Ching-Hua Hsieh, Yi-Yang Lei
  • Publication number: 20240387346
    Abstract: Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge/corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.
    Type: Application
    Filed: August 7, 2023
    Publication date: November 21, 2024
    Inventors: Chih-Chiang Tsao, Chao-Wei Chiu, Hsin Liang Chen, Chia-Shen Cheng, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240389240
    Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chao-Wei Chiu, Chih-Chiang Tsao, Jen-Jui Yu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240379404
    Abstract: A method for handling a semiconductor substrate includes: placing a semiconductor substrate over a semiconductor apparatus, where a central portion of the semiconductor substrate overlies a carrying surface of a chuck table of the semiconductor apparatus, an edge portion of the semiconductor substrate overlies a top surface of a first flexible member of the semiconductor apparatus, the first flexible member is disposed within a recess of the chuck table and extends along a perimeter of the carrying surface, and a gap forms among the semiconductor substrate, the carrying surface of the chuck table, and the top surface of the first flexible member; and introducing a vacuum in vacuum holes in the chuck table to form a vacuum seal among the semiconductor substrate, the chuck table, and the first flexible member.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20240371813
    Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Chih-Chiang Tsao, Hsuan-Ting Kuo, Mao-Yen Chang, Hsiu-Jen Lin, Ching-Hua Hsieh, Hao-Jan Pei
  • Publication number: 20240371827
    Abstract: A package structure includes a supporting base, conductive pillars, a first semiconductor die, a second semiconductor die, a first adhesive material, a second adhesive material and an isolation structure. The conductive pillars are disposed in the supporting base, and protruding out from a top surface of the supporting base. The second semiconductor die is adjacent to the first semiconductor die, wherein the first and second semiconductor dies are disposed on the supporting base and electrically connected to the conductive pillars. The first adhesive material is disposed in between the first semiconductor die and the top surface of the supporting base, and partially covering the conductive pillars. The second adhesive material is disposed in between the second semiconductor die and the top surface of the supporting base, and partially covering the conductive pillars. The isolation structure prevents a bleeding of the first and second adhesive material to an adjacent semiconductor die.
    Type: Application
    Filed: May 3, 2023
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Fung Chang, Ching-Hua Hsieh, Yi-Yang Lei, Chao-Wei Chiu, Ming-Yu Yen
  • Publication number: 20240363388
    Abstract: An adhesion film with a plurality of semiconductor packages thereupon may be positioned on a pedestal including an enclosure and having a perforated top surface, a first support ring located at a periphery of the perforated top surface, and a second support ring laterally surrounding the first support ring. A first semiconductor package overlaps segments of the first support ring at a plurality of overlap areas in a top-down view, and does not contact the second support ring in the top-down view. A vacuum suction may be applied to a volume within the enclosure and to a gap which is vertically bounded by a bottom surface of the adhesion film and is laterally bounded by the first support ring while holding the first semiconductor package stationary. A portion of the adhesion film underlying the first semiconductor package is peeled off a bottom surface of the first semiconductor package.
    Type: Application
    Filed: April 26, 2023
    Publication date: October 31, 2024
    Inventors: Hsin Liang Chen, Ching-Hua Hsieh, Hsiu-Jen Lin, Hsuan-Ting Kuo, Wei-Yu Chen, Cheng-Shiuan Wong
  • Publication number: 20240356199
    Abstract: A method of manufacturing an electronic device includes: providing a composite structure, wherein the composite structure comprises a core dielectric layer with two conductive layers formed on two opposite surfaces of the core dielectric layer; thinning the two conductive layers to form two thinned conductive layers; forming an antenna pattern using one of the two thinned conductive layers; forming an antenna package to encapsulate the antenna pattern therein; forming a circuit pattern by patterning the other one of the two thinned conductive layers; and forming a chip package to encapsulate the circuit pattern therein, wherein the chip package is electrically coupled to the antenna package.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang, Yu-Ting Chiu, Jui-Chang Kuo
  • Publication number: 20240355691
    Abstract: A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.
    Type: Application
    Filed: July 1, 2024
    Publication date: October 24, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin
  • Patent number: 12125797
    Abstract: A package structure is provided. The package structure includes a semiconductor chip and a first dielectric layer over the semiconductor chip and extending across opposite sidewalls of the semiconductor chip. The package structure also includes a conductive layer over the first dielectric layer, and the conductive layer has multiple first protruding portions extending into the first dielectric layer. The package structure further includes a second dielectric layer over the first dielectric layer and the conductive layer. The second dielectric layer has multiple second protruding portions extending into the first dielectric layer. Each of the first protruding portions and the second protruding portions is thinner than the first dielectric layer.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Tsung-Hsien Chiang, Ming-Da Cheng, Ching-Hua Hsieh
  • Publication number: 20240339424
    Abstract: Embodiments provide a device structure and method of forming a device structure including an infill structure to capture solder materials within confines of openings of the infill structure. Metal pillars of one device can penetrate through a non-conductive film and contact solder regions of another device. A separate underfill is not needed.
    Type: Application
    Filed: August 7, 2023
    Publication date: October 10, 2024
    Inventors: Wei-Yu Chen, Chao-Wei Chiu, Hsin Liang Chen, Hao-Jan Pei, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240332132
    Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Sung-Yueh Wu, Chien-Ling Hwang, Ching-Hua Hsieh
  • Publication number: 20240332215
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a redistribution layer (RDL) structure, a passive device, and a plurality of dummy items. The encapsulant laterally encapsulates the die. The RDL structure is disposed on the die and the encapsulant. The passive device is disposed on and electrically bonded to the RDL structure. The plurality of dummy items are disposed on the RDL structure and laterally aside the passive device, wherein top surfaces of the plurality of dummy items are higher than a top surface of the passive device.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Wei-Yu Chen, Chih-Chiang Tsao, Chao-Wei Chiu
  • Patent number: 12107064
    Abstract: A semiconductor package includes a substrate, a semiconductor device over the substrate and a plurality of solder joint structures bonded between the semiconductor device and the substrate, wherein each of the plurality of solder joint structures includes, by weight percent, 2% to 23% of Indium (In).
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Jui Yu, Chih-Chiang Tsao, Hsuan-Ting Kuo, Mao-Yen Chang, Hsiu-Jen Lin, Ching-Hua Hsieh, Hao-Jan Pei
  • Publication number: 20240321848
    Abstract: A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.
    Type: Application
    Filed: June 6, 2024
    Publication date: September 26, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Publication number: 20240312941
    Abstract: An electronic apparatus including a package substrate and a structure disposed on and electrically connected to the package substrate through conductive bumps is provided. The material of the conductive bumps includes a bismuth (Bi) containing alloy or an indium (In) containing alloy. In some embodiments, the bismuth (Bi) containing alloy includes Sn—Ag—Cu—Bi alloy. In some embodiments, a concentration of bismuth (Bi) contained in the Sn—Ag—Cu—Bi alloy ranges from about 1 wt % to about 10 wt %. Methods for forming the Sn—Ag—Cu—Bi alloy are also provided.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Wei Chiu, Wei-Yu Chen, Chih-Chiang Tsao, Hao-Jan Pei, Hsiu-Jen Lin, Ching-Hua Hsieh
  • Publication number: 20240312859
    Abstract: A manufacturing method of a package system includes: providing a base plate with a first thermal interface material (TIM) layer; placing a semiconductor package on the first TIM layer over the base plate, wherein the semiconductor package comprises a plurality of packaging units arranged in an array and a plurality of electrical connectors surrounding the array of the plurality of packaging units; stacking a gasket and a top plate on the array of the plurality of packaging units, wherein the gasket is interposed between the top plate and the array of the plurality of packaging units; and securing the top plate, the gasket, the plurality of packaging units, and the base plate together through a plurality of fasteners, wherein each of the plurality of fasteners is arranged at a gap between two of the adjacent packaging units.
    Type: Application
    Filed: May 26, 2024
    Publication date: September 19, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Ching-Hua Hsieh, Chien-Ling Hwang
  • Publication number: 20240304474
    Abstract: A pickup apparatus for separating a semiconductor package from an adhesive film includes a platform, a roller, a moving mechanism, and a collector element. The platform has a surface disposed with the adhesive film, where the adhesive film is disposed between the platform and the semiconductor package. The roller is disposed inside the platform and under the adhesive film, where the roller includes a body and a plurality of protrusions distributed over the body. The moving mechanism is connected to the roller to control a movement of the roller. The collector element is disposed over the platform and the adhesive film, where the collector element is configured to remove the semiconductor package from the adhesive film.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chun Liao, Ching-Hua Hsieh, Chih-Wei Lin, Hsiao-Chung Liang, Ying-Jui Huang
  • Publication number: 20240293962
    Abstract: A molded semiconductor device includes a semiconductor device and a molding material encapsulating the semiconductor device, wherein an upper surface of the molding material is substantially coplanar with an upper surface of the semiconductor device and comprises a groove at least partially surrounding the upper surface of the semiconductor device.
    Type: Application
    Filed: May 14, 2024
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Feng Weng, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Sheng-Hsiang Chiu, Yao-Tong Lai, Chia-Min Lin