Patents by Inventor Ching-Hua Lee
Ching-Hua Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11942376Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.Type: GrantFiled: August 8, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Chung-Cheng Wu, Clement Hsingjen Wann
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Patent number: 11929422Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.Type: GrantFiled: July 29, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Patent number: 11917955Abstract: Apparatus, systems and methods for irrigating lands are disclosed. In one example, an irrigation system is disclosed. The irrigation system includes a gate and a microcontroller unit (MCU). The gate is configured for adjusting a water flow for irrigating a piece of land. The MCU is configured for controlling the gate to adjust the water flow based on environmental information related to the piece of land.Type: GrantFiled: July 8, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Cheng Huang, Tai-Hua Yu, Shui-Ting Yang, Chao-Te Lee, Ching Rong Lu
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Publication number: 20240046946Abstract: A method includes obtaining, using at least one processing device, noisy speech signals and extracting, using the at least one processing device, acoustic features from the noisy speech signals. The method also includes receiving, using the at least one processing device, a predicted speech mask from a speech mask prediction model based on a first acoustic feature subset and receiving, using the at least one processing device, a predicted noise mask from a noise mask prediction model based on a second acoustic feature subset. The method further includes providing, using the at least one processing device, predicted speech features determined using the predicted speech mask and predicted noise features determined using the predicted noise mask to a filtering mask prediction model. In addition, the method includes generating, using the at least one processing device, a clean speech signal using a predicted filtering mask output by the filtering mask prediction model.Type: ApplicationFiled: November 22, 2022Publication date: February 8, 2024Inventors: Chou-Chang Yang, Ching-Hua Lee, Rakshith Sharma Srinivasa, Yashas Malur Saidutta, Yilin Shen, Hongxia Jin
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Patent number: 11849283Abstract: A method and system or device such as a hearing aid are provided for processing audio signals. In accordance with the method, an audio signal is received and divided into a plurality of frequency sub-bands. For each of the frequency sub-band signals, the signal is further divided into overlapping temporal frames. Each of the temporal frames are windowed. Frequency warping is performed on each of the windowed frames. Overlap-and-add is performed on the frequency warped frames. The frequency warped sub-bands are combined into a full band to provide a frequency warped signal.Type: GrantFiled: September 16, 2020Date of Patent: December 19, 2023Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Harinath Garudadri, Ching-Hua Lee, Kuan-Lin Chen, Fred Harris, Bhaskar Rao
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Publication number: 20230402534Abstract: A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and a gate electrode surrounding the interfacial layer.Type: ApplicationFiled: August 21, 2023Publication date: December 14, 2023Inventors: Ching-Hua Lee, Miao-Syuan Fan, Ta-Hsiang Kung, Jung-Wei Lee
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Patent number: 11695055Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.Type: GrantFiled: March 3, 2020Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Patent number: 11676867Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first conductive region and a second conductive region. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region.Type: GrantFiled: August 9, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Clement Hsingjen Wann, Yu-Ming Lin
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Publication number: 20220384275Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: CHUN HSIUNG TSAI, CHENG-YI PENG, CHING-HUA LEE, CHUNG-CHENG WU, CLEMENT HSINGJEN WANN
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Publication number: 20220384613Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second SID regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Lid.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Publication number: 20220360911Abstract: A method and system or device such as a hearing aid are provided for processing audio signals. In accordance with the method, an audio signal is received and divided into a plurality of frequency sub-bands. For each of the frequency sub-band signals, the signal is further divided into overlapping temporal frames. Each of the temporal frames are windowed. Frequency warping is performed on each of the windowed frames. Overlap-and-add is performed on the frequency warped frames. The frequency warped sub-bands are combined into a full band to provide a frequency warped signal.Type: ApplicationFiled: September 16, 2020Publication date: November 10, 2022Inventors: Harinath GARUDADRI, Ching-Hua LEE, Kuan-Lin CHEN, Fred HARRIS, Bhaskar RAO
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Publication number: 20220328670Abstract: A semiconductor device includes a substrate, a semiconductor structure suspending over the substrate and comprising a source region, a drain region, and a channel region disposed between the source region and the drain region. The channel region includes a doped two-dimensional (2D) material layer comprising a first portion on an upper surface of the channel region. The semiconductor device also includes an interfacial layer surrounding the channel region including the first portion of the doped 2D material layer, and and a gate electrode surrounding the interfacial layer.Type: ApplicationFiled: August 11, 2021Publication date: October 13, 2022Inventors: Ching-Hua Lee, Miao-Syuan Fan, Ta-Hsiang Kung, Jung-Wei Lee
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Patent number: 11450571Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.Type: GrantFiled: May 6, 2019Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Chung-Cheng Wu, Clement Hsingjen Wann
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Publication number: 20220165847Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.Type: ApplicationFiled: February 14, 2022Publication date: May 26, 2022Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.Inventors: Miao-Syuan FAN, Pei-Wei LEE, Ching-Hua LEE, Jung-Wei LEE
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Patent number: 11251268Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.Type: GrantFiled: July 23, 2020Date of Patent: February 15, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Miao-Syuan Fan, Pei-Wei Lee, Ching-Hua Lee, Jung-Wei Lee
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Patent number: 11232953Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.Type: GrantFiled: September 17, 2019Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Miao-Syuan Fan, Ching-Hua Lee, Ming-Te Chen, Jung-Wei Lee, Pei-Wei Lee
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Publication number: 20210375694Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first conductive region and a second conductive region. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region.Type: ApplicationFiled: August 9, 2021Publication date: December 2, 2021Inventors: CHUN HSIUNG TSAI, CHENG-YI PENG, CHING-HUA LEE, CLEMENT HSINGJEN WANN, YU-MING LIN
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Patent number: 11133222Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes the following operations. A substrate is received, and the substrate includes a first transistor with a first conductive region and a second transistor with a second conductive region, wherein the first transistor and the second transistor have different conductive types. A first laser anneal is performed on the first conductive region to repair lattice damage. An amorphization is performed on the first conductive region and the second conductive region to enhance silicide formation to a desired phase transformation in the subsequent operations. A pre-silicide layer is formed on the substrate after the amorphization. A thermal anneal is performed to the substrate to form a silicide layer from the pre-silicide layer. A second laser anneal is performed on the first conductive region and the second conductive region after the formation of the pre-silicide layer.Type: GrantFiled: May 6, 2019Date of Patent: September 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Clement Hsingjen Wann, Yu-Ming Lin
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Publication number: 20210280486Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.Type: ApplicationFiled: March 3, 2020Publication date: September 9, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi PENG, Ching-Hua LEE, Song-Bor LEE
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Publication number: 20210234000Abstract: The present disclosure relates to a semiconductor device includes first and second source/drain (S/D) regions doped with lead (Pb) at a first dopant concentration. The semiconductor device also includes a channel region between the first and second S/D regions, where the channel region is doped with Pb at a second dopant concentration that is lower than the first dopant concentration. The semiconductor device further includes first and second S/D contacts in contact with the first and second S/D regions, respectively. The semiconductor device also includes a gate electrode over the channel region.Type: ApplicationFiled: July 23, 2020Publication date: July 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Miao-Syuan FAN, Pei-Wei LEE, Ching-Hua LEE, Jung-Wei LEE