Patents by Inventor Ching-Huang Wang

Ching-Huang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11531524
    Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Chih-Hui Weng, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang, Chia-Hsiang Chen
  • Publication number: 20220373594
    Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
  • Patent number: 11506706
    Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
  • Publication number: 20220358013
    Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Yu-Der Chih, Ching-Huang Wang, Yi-Chun Shih, Meng-Chun Shih, C. Y. Wang
  • Publication number: 20220328423
    Abstract: The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes a first surface, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a first magnetic field shielding, including a first portion proximal to the third surface of the semiconductor chip, wherein the first portion has a first height calculated from the mounting surface to a top surface, and a second portion distal to the semiconductor chip, has a second height calculated from the mounting surface to a position at a surface facing away from the mounting surface, wherein the second height is less than the first height, wherein the second portion has an inclined sidewall.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 13, 2022
    Inventors: HARRY-HAK-LAY CHUANG, CHIA-HSIANG CHEN, MENG-CHUN SHIH, CHING-HUANG WANG, TIEN-WEI CHIANG
  • Patent number: 11447643
    Abstract: This invention is to provide a hard coating film, comprising a polymethyl methacrylate (PMMA) base film and an antiglare hard coating layer formed thereon, wherein the antiglare hard coating layer comprises a (meth)acrylate composition, an initiator, a plurality of silica nanoparticles, a plurality of organic microparticles and a leveling agent. The (meth)acrylate composition comprises a urethane (meth)acrylate oligomer with a functionality of 6 to 15 and a molecular weight ranging between 1,000 and 4,500, and at least one (meth)acrylate monomer with a functionality of 3 to 6, and at least one (meth)acrylate monomer with functionality of less than 3.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: September 20, 2022
    Assignee: BenQ Materials Corporation
    Inventors: Ching-Huang Chen, Tze-Chi Wang, Kuo-Hsuan Yu, Gang-Lun Fan
  • Patent number: 11429482
    Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Ching-Huang Wang, Yi-Chun Shih, Meng-Chun Shih, C. Y. Wang
  • Patent number: 11380626
    Abstract: The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes: a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a magnetic device disposed in the semiconductor chip, a first magnetic field shielding at least partially surrounding the third surface, a second magnetic field shielding, including a top surface facing the second surface of the semiconductor chip, and a molding surrounding the semiconductor chip, wherein the entire top surface of the second magnetic field shielding is in direct contact with the molding.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang, Tien-Wei Chiang
  • Patent number: 11326052
    Abstract: A biodegradable plastic composition is used to manufacture a biodegradable plastic. The biodegradable plastic composition includes a biodegradable polyester, a polysaccharide, and a modifier. The modifier is used to compound the polysaccharide and the biodegradable polyester to obtain a biodegradable plastic. The biodegradable plastic has a tensile strength greater than 3 MPa and an elongation greater than 81%.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 10, 2022
    Assignees: Tatung Company, TATUNG UNIVERSITY
    Inventors: C. Will Chen, Chun-Yeh Chu, Ping-Hsun Tsai, Ching-Huang Wang, Chiung-Cheng Huang, Tai-Wei Tseng
  • Patent number: 11276649
    Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang
  • Patent number: 11249131
    Abstract: A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Chia Yu Wang, Meng-Chun Shih, Ching-Huang Wang, Chih-Yang Chang, Chia-Hsiang Chen, Chih-Hui Weng
  • Publication number: 20210311105
    Abstract: A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Inventors: HARRY-HAK-LAY CHUANG, TIEN-WEI CHIANG, CHIA YU WANG, MENG-CHUN SHIH, CHING-HUANG WANG, CHIH-YANG CHANG, CHIA-HSIANG CHEN, CHIH-HUI WENG
  • Publication number: 20210173739
    Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Inventors: Yu-Der Chih, Ching-Huang Wang, Yi-Chun Shih, Meng-Chun Shih, C.Y. Wang
  • Publication number: 20210109152
    Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 15, 2021
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
  • Patent number: 10936413
    Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Ching-Huang Wang, Yi-Chun Shih, Meng-Chun Shih, C.Y. Wang
  • Publication number: 20210043582
    Abstract: The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes: a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a magnetic device disposed in the semiconductor chip, a first magnetic field shielding at least partially surrounding the third surface, a second magnetic field shielding, including a top surface facing the second surface of the semiconductor chip, and a molding surrounding the semiconductor chip, wherein the entire top surface of the second magnetic field shielding is in direct contact with the molding.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventors: HARRY-HAK-LAY CHUANG, CHIA-HSIANG CHEN, MENG-CHUN SHIH, CHING-HUANG WANG, TIEN-WEI CHIANG
  • Publication number: 20200411449
    Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.
    Type: Application
    Filed: December 11, 2019
    Publication date: December 31, 2020
    Inventors: Harry-Hak-Lay Chuang, Tien-Wei Chiang, Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang
  • Patent number: 10877089
    Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
  • Patent number: 10818609
    Abstract: The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang, Tien-Wei Chiang
  • Publication number: 20200283621
    Abstract: A biodegradable plastic composition is used to manufacture a biodegradable plastic. The biodegradable plastic composition includes a biodegradable polyester, a polysaccharide, and a modifier. The modifier is used to compound the polysaccharide and the biodegradable polyester to obtain a biodegradable plastic. The biodegradable plastic has a tensile strength greater than 3 MPa and an elongation greater than 81%.
    Type: Application
    Filed: January 9, 2020
    Publication date: September 10, 2020
    Applicants: Tatung Company, TATUNG UNIVERSITY
    Inventors: C. Will Chen, Chun-Yeh Chu, Ping-Hsun Tsai, Ching-Huang Wang, Chiung-Cheng Huang, Tai-Wei Tseng