Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Abstract: The present disclosure provides a package structure, including a mounting pad having a mounting surface, a semiconductor chip disposed on the mounting surface of the mounting pad, wherein the semiconductor chip includes: a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface and facing the mounting surface, and a third surface connecting the first surface and the second surface, a magnetic device disposed in the semiconductor chip, a first magnetic field shielding at least partially surrounding the third surface, a second magnetic field shielding, including a top surface facing the second surface of the semiconductor chip, and a molding surrounding the semiconductor chip, wherein the entire top surface of the second magnetic field shielding is in direct contact with the molding.

Abstract: Devices and methods are provided in which a magnetic sensitive semiconductor chip, such as a magnetoresistive random-access memory (MRAM) chip, is shielded from magnetic interference by a magnetic shielding layer. A device includes a housing that defines an exterior surface. A semiconductor chip is disposed within the housing, and the semiconductor chip is spaced apart from the exterior surface of the housing. A magnetic shielding layer is spaced apart from the semiconductor chip by a distance less than 5 mm.

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

Abstract: The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface.

Abstract: A biodegradable plastic composition is used to manufacture a biodegradable plastic. The biodegradable plastic composition includes a biodegradable polyester, a polysaccharide, and a modifier. The modifier is used to compound the polysaccharide and the biodegradable polyester to obtain a biodegradable plastic. The biodegradable plastic has a tensile strength greater than 3 MPa and an elongation greater than 81%.

Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data sate. The first random bit is then read from the MRAM cell.

Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.

Abstract: The present disclosure provides a package structure, including a semiconductor chip having a magnetic device, wherein the semiconductor chip includes a first surface perpendicular to a thickness direction of the semiconductor chip, a second surface opposite to the first surface, and a third surface connecting the first surface and the second surface, and a first magnetic field shielding at least partially surrounding the third surface.

Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures, the subset of bits comprise compressed code. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

Abstract: In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.

Abstract: A biodegradable polyester is consisting of a poly(terephthalate-di-(?-caprolactone) segment, a poly(terephthalate-butylene-terephthalate) segment, a poly(terephthalate-butylene-?-caprolactone) segment, a poly(?-caprolactone-butylene-?-caprolactone) segment, and a poly(tri(?-caprolactone) segment. The above five segments are obtained by polycondensation reaction of terephthalic acid, 1,4-butanediol and ?-caprolactone under the presence of a catalyst, with a polycondensation temperature of 255° C. to 270° C. and a polycondensation time of 2 hours to 4 hours. Furthermore, based on 1 mole of terephthalic acid, a molar ratio of 1,4-butanediol to terephthalic acid is in the range of 1.1 to 1.4, and a molar ratio of ?-caprolactone to terephthalic acid is in the range of 0.5 to 1.6. The biodegradable polyester can have a melting point (Tm) of 90° C. to 170° C.

Abstract: Systems and methods for correcting data errors in memory caused by high-temperature processing of the memory are provided. An integrated circuit (IC) die including a memory is formed. Addresses of memory locations that are susceptible to data loss when subjected to elevated temperatures are determined. Bits of data are written to the memory, where the bits of data include a set of bits written to the memory locations. The set of bits are written to a storage device of the IC die that is not susceptible to data loss when subjected to the elevated temperatures. At least one of the bits stored at the addresses is overwritten after subjecting the IC die to an elevated temperature. The at least one of the bits is overwritten based on the set of bits written to the storage device.

Abstract: In the present disclosure, a non-volatile memory cell comprises a data storage unit, a selection unit and a switching unit. The data storage unit is configured to store an information bit and has a first end and a second end. The first end is coupled to a bit line. The selection unit is configured to access the data storage unit, and the selection unit has a first end coupled to a select line, a second end coupled to the second end of the data storage unit, and a third end coupled to a source line. The switching unit is configured to perform a formation operation and has a first end coupled to a forming line and a second end coupled to the second end of the data storage unit.

Abstract: A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB.