Patents by Inventor Ching Hui Chen

Ching Hui Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363461
    Abstract: A device including a substrate, a front-end module circuit situated over the substrate and configured to provide radio frequency communications, and a wafer-level chip-scale package circuit situated over the front-end module circuit and connected to the front-end module circuit and configured to provide passive components for radio frequency communications.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Hsieh-Hung Hsieh, Chen Cheng Chou, Hwa-Yu Yang, Ming-Da Cheng, Ru-Shang Hsiao, Tzu-Jin Yeh, Ching-Hui Chen, Shenggao Li
  • Publication number: 20240122338
    Abstract: The present utility model discloses a shelf with lighting effect, which vertically spaces a plurality of mounting frames, connects them respectively among a plurality of upright columns; the said mounting frames are installed with support plates to form a vertical shelf with a plurality of compartments, each of which can be used to hold objects; on the side of the mounting frames is arranged with at least one lamp groove, and in the lamp grooves are arranged with LED light strips electrically connected with the power supply subassembly to provide lighting effect for the objects placed on the support plates.
    Type: Application
    Filed: November 23, 2022
    Publication date: April 18, 2024
    Inventor: Ching-Hui CHEN
  • Patent number: 11908818
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
  • Publication number: 20230369049
    Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 16, 2023
    Inventors: Chang-Jung Hsueh, Chen-En Yen, Chin Wei Kang, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii
  • Publication number: 20230359865
    Abstract: The present disclosure provides systems, methods, and computer program products for modeling dependencies throughout a network using a global-self attention model with a content attention layer and a positional attention layer that operate in parallel. The model receives input data comprising content values and context positions. The content attention layer generates one or more output features for each context position based on a global attention operation applied to the content values independent of the context positions. The positional attention layer generates an attention map for each of the context positions based on one or more content values of the respective context position and associated neighboring positions. Output is determined based on the output features generated by the content attention layer and the attention map generated for each context position by the positional attention layer. The model improves efficiency and can be used throughout a deep network.
    Type: Application
    Filed: September 16, 2020
    Publication date: November 9, 2023
    Inventors: Zhuoran Shen, Raviteja Vemulapalli, Irwan Bello, Xuhui Jia, Ching-Hui Chen
  • Patent number: 11812646
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: November 7, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Publication number: 20230281979
    Abstract: Systems and methods of the present disclosure are directed to a method for training a machine-learned visual attention model. The method can include obtaining image data that depicts a head of a person and an additional entity. The method can include processing the image data with an encoder portion of the visual attention model to obtain latent head and entity encodings. The method can include processing the latent encodings with the visual attention model to obtain a visual attention value and processing the latent encodings with a machine-learned visual location model to obtain a visual location estimation. The method can include training the models by evaluating a loss function that evaluates differences between the visual location estimation and a pseudo visual location label derived from the image data and between the visual attention value and a ground truth visual attention label.
    Type: Application
    Filed: August 3, 2020
    Publication date: September 7, 2023
    Inventors: Xuhui Jia, Raviteja Vemulapalli, Bradley Ray Green, Bardia Doosti, Ching-Hui Chen
  • Patent number: 11742204
    Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: August 29, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Jung Hsueh, Chen-En Yen, Chin Wei Kang, Kai Jun Zhan, Wei-Hung Lin, Cheng Jen Lin, Ming-Da Cheng, Ching-Hui Chen, Mirng-Ji Lii
  • Publication number: 20230213155
    Abstract: The present utility model discloses a column and a combined lamp equipped with the column, the column in the present utility model can be formed by a single column body or formed by a plurality of columns which are connected in a vertically adjacent manner; the LED light strips on two adjacent columns can be connected via the conductive subassembly; when the column is used to form the frame of the combined lamp, the LED light strip(s) arranged on the column body can be used for lighting to increase the illumination intensity of the combined lamp and the diversity of the frame of the combined lamp and thus improve the practicability of the combined lamp.
    Type: Application
    Filed: November 18, 2022
    Publication date: July 6, 2023
    Inventor: Ching-Hui CHEN
  • Publication number: 20230214656
    Abstract: At training time, a base neural network can be trained to perform each of a plurality of basis subtasks included in a total set of basis subtasks (e.g., individually or some combination thereof). Next, a description of a desired combined subtask can be obtained. Based on the description of the combined subtask, a mask generator can produce a pruning mask which is used to prune the base neural network into a smaller combined-subtask-specific network that performs only the two or more basis subtasks included in the combined subtask.
    Type: Application
    Filed: June 10, 2020
    Publication date: July 6, 2023
    Inventors: Raviteja Vemulapalli, Jianrui Cai, Bradley Ray Green, Ching-Hui Chen, Lior Shapira
  • Patent number: 11594484
    Abstract: A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the second dielectric layer to form a first opening, with a top surface of the first dielectric layer exposed to the first opening. A template layer is formed to fill the first opening. A second opening is then formed in the template layer and the first dielectric layer, with a top surface of the conductive pad exposed to the second opening. A conductive pillar is formed in the second opening.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mirng-Ji Lii, Chung-Shi Liu, Chin-Yu Ku, Hung-Jui Kuo, Alexander Kalnitsky, Ming-Che Ho, Yi-Wen Wu, Ching-Hui Chen, Kuo-Chio Liu
  • Patent number: 11566772
    Abstract: The present utility model discloses a lampshade comprising fasteners, a lampshade body and support frames; the lampshade body comprises a light transmitting sheet and a piece of lampshade cloth; the bottom and/or top of the lampshade body are/is designed with soft band-shaped reinforcing ribs which extend in the length direction of the side wall surface and cover the lampshade body and prop up against at least one fastener; in the present utility model, the bottom and/or top of the lampshade body are/is designed with soft band-shaped reinforcing ribs which extend in the length direction of the side wall surface, the integration of the reinforcing ribs and the matching fasteners with the flexibility of the soft material makes the lampshade easy to be packaged and reduce the volume of its package and finally lower the transportation cost.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 31, 2023
    Inventor: Ching-Hui Chen
  • Publication number: 20220368012
    Abstract: A method of manufacturing a semiconductor device including operations including the operations of forming a ground plane over a substrate, forming a first conductive pillar in contact with the ground plane and attaching a die to the substrate, electrically isolating the die from the first conductive pillar with a dielectric fill material, forming a dielectric pad of a high-? dielectric material (having a ? of at least 7 Farads/meter) at an end of the first conductive pillar opposite the ground plane, forming an antenna pad over the dielectric pad, and establishing an electrical connection between the antenna pad and the die.
    Type: Application
    Filed: July 22, 2022
    Publication date: November 17, 2022
    Inventors: Feng Wei KUO, Wen-Shiang LIAO, Ching-Hui CHEN
  • Patent number: 11502402
    Abstract: A device includes a ground plane electrically connected to a proximal end of at least one conductive pillar and an antenna pad substantially parallel to the ground plane, wherein the antenna pad is separated from a distal end of the at least one conductive pillar by a dielectric pad having a first dielectric constant, wherein the ground plane, the at least one conductive pillar, and the dielectric pad surround an antenna cavity filled with a dielectric fill material having a second dielectric constant different from the first dielectric constant.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, Wen-Shiang Liao, Ching-Hui Chen
  • Patent number: D986654
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: May 23, 2023
    Inventor: Ching-Hui Chen
  • Patent number: D1030374
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: June 11, 2024
    Inventor: Ching-Hui Chen
  • Patent number: D1040567
    Type: Grant
    Filed: August 1, 2021
    Date of Patent: September 3, 2024
    Inventor: Ching-Hui Chen
  • Patent number: D1070433
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 15, 2025
    Inventor: Ching-Hui Chen
  • Patent number: D1070434
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: April 15, 2025
    Inventor: Ching-Hui Chen
  • Patent number: D1070435
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: April 15, 2025
    Inventor: Ching-Hui Chen