Patents by Inventor Ching Hung

Ching Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149379
    Abstract: A method includes following steps. A semiconductor fin is formed on a substrate. A shallow trench isolation (STI) region is formed around a lower portion of the semiconductor fin. An STI protection layer is over the STI region. After forming the STI protection layer, source/drain recesses are etched in the semiconductor fin. Source/drain epitaxial regions are formed in the source/drain recesses.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Hung CHEN, Yen-Chun HUANG, Yu-Wei CHOU, Zhen-Cheng WU
  • Patent number: 12288801
    Abstract: A semiconductor structure includes a first dielectric layer, a conductive layer over the first dielectric layer, and a first electrode over a first portion of the conductive layer. A first thickness of the first portion of the conductive layer is greater than a second thickness of a second portion of the conductive layer not under the first electrode.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTUING COMPANY LIMITED
    Inventor: Ching-Hung Kao
  • Publication number: 20250126936
    Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer includes an upper surface; a plurality of exposed regions, formed in the semiconductor stack and exposing the upper surface; a lower protective layer, covering the exposed regions and the second semiconductor layer; a first reflective structure, formed on the second semiconductor layer and including a plurality of first openings on the second semiconductor layer; a second reflective structure, formed on the first reflective structure and electrically connected to the second semiconductor layer through the plurality of first openings; and an upper protective layer, formed on the second reflective structure; wherein the upper protective layer contacts and overlaps the lower protective layer on the exposed regions; wherein the first reflective structure and the
    Type: Application
    Filed: December 17, 2024
    Publication date: April 17, 2025
    Inventors: Jhih-Yong YANG, Hsin-Ying WANG, De-Shan KUO, Chao-Hsing CHEN, Yi-Hung LIN, Meng-Hsiang HONG, Kuo-Ching HUNG, Cheng-Lin LU
  • Publication number: 20250121920
    Abstract: A biomimetic turtle includes a trunk, a head movably connected with a front end of the trunk in the front-rear direction, two front limbs disposed on a front section of the trunk and each rotatable relative to the trunk to sway in an up-down direction, and a driving module to drive the head and the front limbs. Each front limb has a curve-shaped rigid portion with a recess, and a deformable flipper portion engaged in the recess and extending rearwardly. With the deformable flipper portion deformed and bent during swaying of the front limbs, a forward propelling force is generated to propel the biomimetic turtle forwardly. The head is operably movable to vary the center of gravity of 10 the biomimetic turtle 100 in the water, and thus the front portion of the biomimetic turtle is inclined upwardly or downwardly to facilitate ascending or descending of the biomimetic turtle.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 17, 2025
    Inventors: Wei-Yu HUANG, Chang-Qi ZHANG, Guan-Hao PAN, Li-Yuan YEH, Tai-Yu CHEN, Ching-Hung LIU, Jian-Jhih HUANG, Ching-Shu LAI
  • Patent number: 12278211
    Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.
    Type: Grant
    Filed: October 23, 2023
    Date of Patent: April 15, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Jen Lo, Hsih Yang Chiu, Ching Hung Chang, Chiang-Lin Shih
  • Patent number: 12274054
    Abstract: A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shun-Neng Wang, Tung-Huang Chen, Ching-Hung Kao
  • Patent number: 12266684
    Abstract: A method of forming a capacitor is disclosed. The method includes forming a portion of a metallization layer on a substrate, forming a via layer on the substrate, and forming a first electrode between the metallization layer and the via layer, where the first electrode is electrically connected to the metallization layer. The method also includes forming a second electrode between the metallization layer and the via layer, where the second electrode is electrically connected to the via layer, and forming a dielectric layer between the first electrode and the second electrode, where the first electrode is not electrically connected to any other conductors other than through the metallization layer, and where the second electrode is not electrically connected to any conductors other than through the via layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
    Inventors: Pei-Jen Wang, Ching-Hung Kao, Tzy-Kuang Lee, Meng-Chang Ho, Kun-Mao Wu
  • Publication number: 20250105180
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes an interconnect structure on a substrate; a passivation layer disposed on the interconnect structure; a first via, a second via and a third via disposed in the passivation layer and connected to the interconnect structure, each of the first, second and third vias has an elongated shape longitudinally oriented along a first direction; and a first pad longitudinally oriented along the first direction and landing on the first, second and third vias.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Ching-Hung Kao, Kuei-Yu Deng
  • Patent number: 12261397
    Abstract: This disclosure is directed to an electrical connector having an insulative seat, a first terminal group and a second terminal group. The first terminal group has first terminals embedded in the insulative seat, the first terminals are separated from each other, and each first terminal has a first wiring end. The second terminal group is separated from the first terminal group, the second terminal group has second terminals and a connecting strip, the second terminals are embedded in the insulative seat, each second terminal has a second wiring end. The first and the second terminals are arranged on a reference plane, the first and the second terminals protrude from one side of the insulative seat, and the second terminals are bent to deviate from the reference plane, and the connecting strip is connected with the second terminals to make the second terminals be electrically connected with each other.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 25, 2025
    Assignee: JESS-LINK PRODUCTS CO., LTD.
    Inventors: Ching-Hung Liu, Ming-Yang Yuan
  • Patent number: 12256845
    Abstract: Apparatuses, components, devices, methods, and systems for an adjustable firmness mattress are provided. An example rectangular shaped adjustable firmness mattress extends lengthwise from a head end to a foot end, widthwise from a first side to a second side, and depth-wise from a top side to a bottom side. The example mattress may include an adjustable firmness support layer disposed between the bottom side of the mattress and the top side of the mattress. The adjustable firmness support layer may include at least one rotatable assembly having an orientation-specific firmness, a bridge assembly disposed between the at least one rotatable assembly and the top side of the mattress; and a support assembly disposed between the at least one rotatable assembly and the bottom side of the mattress.
    Type: Grant
    Filed: January 29, 2022
    Date of Patent: March 25, 2025
    Inventors: Philip J Haarstad, Molly Haarstad, Alexander Haarstad, Benjamin Haarstad, Connie Marie Haarstad, Donald Melvin Haarstad, Laura K Y Haarstad, Lucas G Haarstad, Paul A Haarstad, Dennis Nathaniel Harvey, Anthony Todd Hessburg, Ching Hung, Heidi J Hung, Shawn M Patterson, Elizabeth Kate Radzwill, Rockford Kenneth White
  • Publication number: 20250085815
    Abstract: Disclosed is an electronic device including a display module, a touch light-emitting module, and a processing unit. The touch light-emitting module includes a light-transmitting unit, a touch unit, and a light-emitting unit. The touch unit is disposed under the light-transmitting unit and is adapted to generate a touch signal based on touch of the user on the light-transmitting unit. The light-emitting unit is disposed on the touch unit. The light-emitting unit is adapted to provide an illumination beam to the light-transmitting unit according to an illumination signal. The processing unit is electrically connected to the display module and the touch light-emitting module. When the electronic device is switched to a touch mode, the processing unit disables the light-10 emitting unit. When the electronic device is switched to a content input mode, the processing unit enables the light-emitting unit to provide the illumination beam to the light-transmitting unit.
    Type: Application
    Filed: September 12, 2024
    Publication date: March 13, 2025
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Hsiao-Ching Hung, Yi-Chia Lee, Yu-Wen Cheng, Wang-Hung Yeh, Hong-Tien Wang
  • Publication number: 20250064224
    Abstract: Apparatuses, components, devices, methods, and systems for an adjustable firmness mattress are provided. An example rectangular shaped adjustable firmness mattress extends lengthwise from a head end to a foot end, widthwise from a first side to a second side, and depth-wise from a top side to a bottom side. The example mattress may include an adjustable firmness support layer disposed between the bottom side of the mattress and the top side of the mattress. The adjustable firmness support layer may include at least one rotatable assembly having an orientation-specific firmness, a bridge assembly disposed between the at least one rotatable assembly and the top side of the mattress; and a support assembly disposed between the at least one rotatable assembly and the bottom side of the mattress.
    Type: Application
    Filed: November 13, 2024
    Publication date: February 27, 2025
    Inventors: Philip J Haarstad, Molly Haarstad, Alexander Haarstad, Benjamin Haarstad, Connie Marie Haarstad, Donald Melvin Haarstad, Laura K Y Haarstad, Lucas G Haarstad, Paul A Haarstad, Dennis Nathaniel Harvey, Anthony Todd Hessburg, Ching Hung, Heidi J Hung, Shawn M Patterson, Elizabeth Kate Radzwill, Rockford Kenneth White
  • Publication number: 20250072189
    Abstract: A display panel includes a substrate and a plurality of pixel structures disposed on the substrate. Each of the pixel structures includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is disposed on the substrate and configured to generate a first colored light. A light output surface of the first light-emitting element includes a combined region. The second light-emitting element is disposed on a part of the combined region and configured to generate a second colored light. The third light-emitting element is disposed on the other part of the combined region and configured to generate a third colored light.
    Type: Application
    Filed: July 19, 2024
    Publication date: February 27, 2025
    Inventors: Hung Lung Chen, Wen Ching Hung, Jr-Hau HE, Chun-wei TSAI, Zhi Ting Ye, Der-Hsien Lien, YUK TONG CHENG
  • Patent number: 12230740
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer and an active area between the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer including an upper surface; an exposed region formed in the semiconductor stack to expose the upper surface; a first protective layer covering the exposed region and a portion of the second semiconductor layer, wherein the first protective layer includes a first part with a first thickness formed on the upper surface and a second part with a second thickness formed on the second semiconductor layer, the first thickness is smaller than the second thickness; a first reflective structure formed on the second semiconductor layer and including one or multiple openings; and a second reflective structure formed on the first reflective structure and electrically connected to the second semiconductor layer through the one or multiple openings.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: February 18, 2025
    Assignee: EPISTAR CORPORATION
    Inventors: Jhih-Yong Yang, Hsin-Ying Wang, De-Shan Kuo, Chao-Hsing Chen, Yi-Hung Lin, Meng-Hsiang Hong, Kuo-Ching Hung, Cheng-Lin Lu
  • Patent number: 12226958
    Abstract: A part formed by an additive manufacturing process consist of regions of voids, regions of solid material, and regions of non-uniform lattice cells, where each lattice cell includes bars. The regions are spatially distributed throughout the part as a function of load conditions such that the solid material is distributed in regions of first load paths and the non-uniform lattice cells are distributed in regions of second load paths lower in magnitude than the first load paths. Diameters of each bar of a non-uniform lattice cell are sized as a function of at least one of a resolution unit of the additive manufacturing process and part performance requirements. The diameters of the bars of the non-uniform lattice cells are classified into clusters with an average diameter size being assigned to all non-uniform lattice cells in the same cluster.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: February 18, 2025
    Assignee: Ford Global Technologies, LLC
    Inventors: Hongyi Xu, Siddharthan Selvasekar, Ching-Hung Chuang, Ellen Lee
  • Patent number: 12230744
    Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,
    Type: Grant
    Filed: September 20, 2023
    Date of Patent: February 18, 2025
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Cheng-Lin Lu, Chih-Hao Chen, Chi-Shiang Hsu, I-Lun Ma, Meng-Hsiang Hong, Hsin-Ying Wang, Kuo-Ching Hung, Yi-Hung Lin
  • Patent number: 12230585
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. An alignment process is performed on a first semiconductor workpiece and a second semiconductor workpiece by virtue of a plurality of workpiece pins. The first semiconductor workpiece is bonded to the second semiconductor workpiece. A shift value is determined between the first and second semiconductor workpieces by virtue of a first plurality of alignment marks on the first semiconductor workpiece and a second plurality of alignment marks on the second semiconductor workpiece. A layer of an integrated circuit (IC) structure is formed over the second semiconductor workpiece based at least in part on the shift value.
    Type: Grant
    Filed: January 24, 2024
    Date of Patent: February 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
  • Publication number: 20250049316
    Abstract: An optical biometer includes a light-source module, a light-splitting module, a reference-arm, a sensing-arm and a sensing module. The light-source module emits incident-light. The light-splitting module, disposed corresponding to light-source module, divides the incident-light into reference light and sensing light. The reference-arm, disposed corresponding to light-splitting module, generates a first reflected-light according to the reference light. The sensing-arm, disposed corresponding to the light-splitting module, emits the sensing light to the eye and receives a second reflected-light from the eye. The sensing module generates a sensing result according to the first reflected-light and second reflected-light. In a first mode, the sensing light is emitted to a first position of the eye. In a second mode, the sensing light is emitted to a second position of the eye.
    Type: Application
    Filed: August 2, 2024
    Publication date: February 13, 2025
    Inventors: Yen-Jen CHANG, Tung-Yu LEE, Chun-Nan LIN, Che-Liang TSAI, Sung-Yang WEI, Hsuan-Hao CHAO, William WANG, Ching Hung LIN
  • Patent number: 12218471
    Abstract: An electrical connector and a cable grounding structure thereof are disclosed. A grounding structure is bridged between a connection body of the electrical connector and each cable, and includes a bridging portion, at least one clamping portion, at least one docking portion, and an elastic portion. The clamping portion is disposed on the bridging portion for clamping a covering layer of each cable, and the docking portion is extended from the bridging portion toward the connection body and electrically connected to connection body, and the elastic portion is attached and pressed against the covering layer of each cable, so as to provide good grounding contact and prevent the issue of skewing the cables and other factors that affects the soldering yield.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: February 4, 2025
    Assignee: JESS-LINK PRODUCTS CO., LTD.
    Inventors: Ching-Hung Liu, Ming-Yang Yuan
  • Patent number: 12216446
    Abstract: A ballbar testing tune-up method for machine tool includes the steps of letting a machine tool system execute a ballbar test; obtaining a phase characteristic and a peak-value characteristic; creating a Lagrange interpolation polynomial and inputting a servo controller parameter, a phase characteristic and a peak-value characteristic of the machine tool system each time when executing the ballbar test, and obtaining a proposed servo parameter. This method is simple and easy without incurring additional equipment costs, but just using existing equipment to find the proposed servo parameter quickly and input it into a machine tool system, so as to improve the response issue of a servo system and reduce manufacturing contour error to enhance the working precision of the machine tool system.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 4, 2025
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Ching-Hung Lee, Shun-Fu Wu