Abstract: A lithography system is provided and includes a light source device configured to emit a processing light beam onto the semiconductor wafer, to generate a penetrating light beam and a reflected light beam. The lithography system further includes a detecting module having a first detector and a second detector. The first detector is configured to receive the penetrating light beam to generate first power data, and the second detector is configured to receive the reflected light beam to generate second power data. The lithography system also includes a monitoring device configured to calculate absorbed power data of the semiconductor wafer according to the first power data, the second power data and reference power data of a reference light beam and configured to compensate for a pattern formed on the semiconductor wafer resulting from the processing light beam according to the absorbed power data and reference information.

Abstract: A reticle stage is provided, including an electrostatic chuck and an acoustic wave transducer. The electrostatic chuck includes multiple chucking electrodes embedded in a dielectric body and configured to secure a reticle to a chuck surface of the dielectric body by electrostatic attraction. The acoustic wave transducer is disposed on the chuck surface and configured to impart a surface acoustic wave to the chuck surface to vibrate the chuck surface, thereby removing the reticle from the reticle stage.

Abstract: A method includes the following operations. A reference image of a mask having a plurality of mapping marks is acquired. A lithography exposing process is performed by a scanner with the mask to a photoresist layer which is formed on a substrate. Performing the lithography exposing process includes mapping a real-time image of the mask with the reference image of the mask.

Abstract: A lithography system is provided and includes a light source device configured to emit a processing light beam onto the semiconductor wafer, to generate a penetrating light beam and a reflected light beam. The lithography system further includes a detecting module having a first detector and a second detector. The first detector is configured to receive the penetrating light beam to generate first power data, and the second detector is configured to receive the reflected light beam to generate second power data. The lithography system also includes a monitoring device configured to calculate absorbed power data of the semiconductor wafer according to the first power data, the second power data and reference power data of a reference light beam and configured to compensate for a pattern formed on the semiconductor wafer resulting from the processing light beam according to the absorbed power data and reference information.

Abstract: A reticle stage is provided, including an electrostatic chuck and an acoustic wave transducer. The electrostatic chuck includes multiple chucking electrodes embedded in a dielectric body and configured to secure a reticle to a chuck surface of the dielectric body by electrostatic attraction. The acoustic wave transducer is disposed on the chuck surface and configured to impart a surface acoustic wave to the chuck surface to vibrate the chuck surface, thereby removing the reticle from the reticle stage.

Abstract: A particle removal apparatus is provided. The particle removal apparatus includes a reticle holder configured to hold a reticle. The particle removal apparatus further includes a robotic arm. The particle removal apparatus also includes a particle removal device disposed on the robotic arm, and the particle removal device includes a solution spraying module. In addition, the robotic arm and the particle removal device are configured to align with a particle on a backside of the reticle, and the solution spraying module is configured to spray a solution onto the particle to remove the particle.

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value.

Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value.