Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a processing chamber; a wafer stage configured in the processing chamber, the wafer stage is operable to secure and rotate a plurality of wafers around an axis; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector.

Abstract: The semiconductor device structures are provided. The semiconductor device structure includes a gate stack structure formed on a substrate and an isolation structure formed in the substrate. The semiconductor device structure further includes a source/drain stressor structure formed between the gate stack structure and the isolation structure and a metal silicide layer formed on the source/drain stressor structure. A portion of the metal silicide layer is below a top surface of the isolation structure.

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.

Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a substrate and forming an isolation structure in the substrate. The method also includes forming a gate stack structure on the substrate and etching a portion of the substrate to form a recess in the substrate, and the recess is adjacent to the gate stack structure. The method includes forming a stressor layer in the recess, and a portion of the stressor layer is grown along the (311) and (111) crystal orientations.

Abstract: An apparatus for processing a semiconductor wafer includes a factory interface configured to couple with a manufacturing chamber. The factory interface includes a robot; an orienter adjacent to the robot; and a particle remover above the orienter and facing toward a wafer. The particle remover is configured to blow ionized gas on a surface of the wafer so as to remove particles.

Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.

Abstract: Embodiments for forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stack structure. The semiconductor device structure further includes an isolation structure formed in the substrate and a source/drain stressor structure formed adjacent to the isolation structure. The source/drain stressor structure includes a capping layer which is formed along the (311) and (111) crystal orientations.

Abstract: A method for forming a composite dielectric layer within a microelectronic product provides a first dielectric layer formed over a substrate of a fluorosilicate glass (FSG) dielectric material deposited employing a high density plasma chemical vapor deposition (HDP-CVD) method. The method also provides a second dielectric layer formed over the first dielectric layer and formed of an undoped silicate glass (USG) dielectric material deposited employing a HDP-CVD source radio frequency power only method employing a source radio frequency power of from about 1000 to about 5000 watts absent a bias power. The composite dielectric layer is formed with inhibited cracking.

Abstract: A method for forming a composite dielectric layer within a microelectronic product provides a first dielectric layer formed over a substrate of a fluorosilicate glass (FSG) dielectric material deposited employing a high density plasma chemical vapor deposition (HDP-CVD) method. The method also provides a second dielectric layer formed over the first dielectric layer and formed of an undoped silicate glass (USG) dielectric material deposited employing a HDP-CVD source radio frequency power only method employing a source radio frequency power of from about 1000 to about 5000 watts absent a bias power. The composite dielectric layer is formed with inhibited cracking.