Patents by Inventor Ching-Lun Lai

Ching-Lun Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240332018
    Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Chih Yung HUNG, Wei-Jen LO, Cheng-Han LEE, Ching-Lun LAI, Chien-Feng LIN, Shahaji B. MORE, Shih-Chieh CHANG
  • Patent number: 12068317
    Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Chen Ho, Chien Lin, Tzu-Wei Lin, Ju Ru Hsieh, Ching-Lun Lai, Ming-Kai Lo
  • Patent number: 12009208
    Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Yung Hung, Shahaji B. More, Chien-Feng Lin, Cheng-Han Lee, Shih-Chieh Chang, Ching-Lun Lai, Wei-Jen Lo
  • Patent number: 11715639
    Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chun Sie, Po-Yi Tseng, Chien-Hao Chen, Ching-Lun Lai, David Sung, Ming-Feng Hsieh, Yi-Chi Huang
  • Publication number: 20230143537
    Abstract: In some implementations, a control device may determine a spacing measurement in a first dimension between a wafer on a susceptor and a pre-heat ring of a semiconductor processing tool and/or a gapping measurement in a second dimension between the wafer and the pre-heat ring, using one or more images captured in situ during a process by at least one optical sensor. Accordingly, the control device may generate a command based on a setting associated with the process being performed by the semiconductor processing tool and the spacing measurement and/or the gapping measurement. The control device may provide the command to at least one motor to move the susceptor.
    Type: Application
    Filed: January 10, 2022
    Publication date: May 11, 2023
    Inventors: Yan-Chun LIU, Yii-Chi LIN, Shahaji B. MORE, Chih-Yu MA, Sheng-Jang LIU, Shih-Chieh CHANG, Ching-Lun LAI
  • Publication number: 20220392767
    Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.
    Type: Application
    Filed: December 8, 2021
    Publication date: December 8, 2022
    Inventors: Chih Yung Hung, Shahaji B. More, Chien-Feng Lin, Cheng-Han Lee, Shih-Chieh Chang, Ching-Lun Lai, Wei-Jen Lo
  • Publication number: 20220246609
    Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Yi-Chen HO, Chien LIN, Tzu-Wei LIN, Ju Ru HSIEH, Ching-Lun LAI, Ming-Kai LO
  • Patent number: 11315921
    Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chen Ho, Chien Lin, Tzu-Wei Lin, Ju Ru Hsieh, Ching-Lun Lai, Ming-Kai Lo
  • Patent number: 11183405
    Abstract: A semiconductor manufacturing apparatus includes an air distributor inside a chamber. The air distributor includes a first annular plate and a second annular plate disposed in an interior volume of the chamber, and an inner surface of the first annular plate and an inner surface of the second annular plate are connected to each other. A hollow region is defined by the first annular plate and the second annular plate. A gas through hole is extended from an outer surface of the first annular plate to the inner surface of the first annular plate. A plurality of ditches are between the inner surface of the first annular plate and the inner surface of the second annular plate, wherein the ditches are connected with the gas through hole and extended from the gas through hole to the hollow region to blow gas toward the hollow region.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Tzung Tsai, Tzu Ken Lin, I-Chang Wu, Ching-Lun Lai, Li-Jia Liou
  • Publication number: 20210193653
    Abstract: An integrated circuit die includes a FinFET transistor. The FinFET transistor includes an anti-punch through region below a channel region. Undesirable dopants are removed from the anti-punch through region during formation of the source and drain regions. When source and drain recesses are formed, a layer of dielectric material is deposited in the recesses. An annealing process is then performed. Undesirable dopants diffuse from the anti-punch through region into the layer of dielectric material during the annealing process. The layer of dielectric material is then removed. The source and drain regions are then formed by depositing semiconductor material in the recesses.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Inventors: Yi-Chen HO, Chien LIN, Tzu-Wei LIN, Ju Ru HSIEH, Ching-Lun LAI, Ming-Kai LO
  • Patent number: 11008654
    Abstract: A semiconductor fabrication apparatus includes a processing chamber; a wafer stage configured in the processing chamber; and a chemical delivery mechanism configured in the processing chamber to provide a chemical to a reaction zone in the processing chamber. The chemical delivery mechanism includes an edge chemical injector, a first radial chemical injector, and a second radial chemical injector configured on three sides of the reaction zone.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20200095682
    Abstract: A semiconductor fabrication apparatus includes a processing chamber; a wafer stage configured in the processing chamber; and a chemical delivery mechanism configured in the processing chamber to provide a chemical to a reaction zone in the processing chamber. The chemical delivery mechanism includes an edge chemical injector, a first radial chemical injector, and a second radial chemical injector configured on three sides of the reaction zone.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 10494716
    Abstract: A semiconductor fabrication apparatus includes a processing chamber; a wafer stage configured in the processing chamber; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and air edge mechanisms configured on both sides of the first reaction zone to isolate the first reaction zone from other reaction zones in the processing chamber.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Publication number: 20190244841
    Abstract: A semiconductor manufacturing apparatus includes an air distributor inside a chamber. The air distributor includes a first annular plate and a second annular plate disposed in an interior volume of the chamber, and an inner surface of the first annular plate and an inner surface of the second annular plate are connected to each other. A hollow region is defined by the first annular plate and the second annular plate. A gas through hole is extended from an outer surface of the first annular plate to the inner surface of the first annular plate. A plurality of ditches are between the inner surface of the first annular plate and the inner surface of the second annular plate, wherein the ditches are connected with the gas through hole and extended from the gas through hole to the hollow region to blow gas toward the hollow region.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Inventors: CHAO-TZUNG TSAI, TZU KEN LIN, I-CHANG WU, CHING-LUN LAI, LI-JIA LIOU
  • Publication number: 20190136378
    Abstract: A semiconductor fabrication apparatus includes a processing chamber; a wafer stage configured in the processing chamber; a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber; and air edge mechanisms configured on both sides of the first reaction zone to isolate the first reaction zone from other reaction zones in the processing chamber.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 10269599
    Abstract: A semiconductor manufacturing apparatus includes a chamber, a view port window on a sidewall of the chamber and configured to receive an optical emission spectroscopy (OES); and an air distributor located between the view port window and an inner space of the chamber. The air distributor includes a hollow region aligned with the transparent window and configured to generate an air curtain in the hollow region to isolate the view port from the inner space.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chao-Tzung Tsai, Tzu Ken Lin, I-Chang Wu, Ching-Lun Lai, Li-Jia Liou
  • Patent number: 10161039
    Abstract: A semiconductor fabrication apparatus includes a processing chamber, a wafer stage configured in the processing chamber, a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber, and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector both configured to deliver the second chemical to the second reaction zone.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee
  • Patent number: 10043892
    Abstract: A method for manufacturing a semiconductor device is provided, including forming a fin field effect transistor (FinFET) structure on a semiconductor substrate. The FinFET structure includes at least one fin, and a gate electrode structure and source/drain regions on the at least one fin. A dielectric film is formed over the at least on fin. The dielectric film is irradiated with ultra violet (UV) radiation from a single UV source.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ying Li, Ming-Shiou Kuo, Wei-Ching Wu, Zong-Han Li, Ching-Lun Lai
  • Publication number: 20180151372
    Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 31, 2018
    Inventors: Yuan-Chun SIE, Po-Yi TSENG, Chien-Hao CHEN, Ching-Lun LAI, David SUNG, Ming-Feng HSIEH, Yi-Chi HUANG
  • Publication number: 20180142351
    Abstract: A semiconductor fabrication apparatus includes a processing chamber, a wafer stage configured in the processing chamber, a first chemical delivery mechanism configured in the processing chamber to provide a first chemical to a first reaction zone in the processing chamber, and a second chemical delivery mechanism configured in the processing chamber to provide a second chemical to a second reaction zone in the processing chamber. The second chemical delivery mechanism includes an edge chemical injector and a first radial chemical injector both configured to deliver the second chemical to the second reaction zone.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 24, 2018
    Inventors: Anthony Lin, Ching-Lun Lai, Pei-Ren Jeng, Tze-Liang Lee