Abstract: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer.

Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.

Abstract: A chip structure, a chip bonding structure, and manufacturing methods thereof are provided. The chip structure includes a chip, a plurality of bumps, and an insulation layer. The bumps are disposed on the chip. Each bump has a first bump portion and a second bump portion connected to each other, wherein the first bump portion and the second bump portion have different activities. The bumps are subjected to chemical reaction to form an insulation layer on the surface of one of the first bump portion and the second bump portion which has higher activity, so as to avoid short-circuit between the adjacent bumps.

Abstract: A die structure and a die connecting method using the same are provided. The die structure includes a die and a bump structure. The bump structure includes a body and a solder layer. The body is disposed on the die. The solder layer is disposed on the body. The method includes providing a die structure mentioned above, providing a circuit board mentioned above, and soldering the solder layer of the die structure with the tine layer on the copper block of the circuit board. In different embodiments, a tin layer is omitted from the circuit board, wherein the solder layer of the die structure is directly soldered onto the surface of the copper block.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: A semiconductor structure and a manufacture method thereof are disclosed. The semiconductor structure includes a semiconductor wafer having a plurality of semiconductor device dies, wherein each of the semiconductor device dies includes a die body, a metal wiring layer, a bump, and a metal layer. The metal wiring layer is formed on the die body while the bump is formed on the metal wiring layer during the semiconductor front-end-of-line (FEOL) process and protrudes from the die body. The metal layer is disposed on one side of the bump opposite to the metal wiring layer, wherein the activity of the metal layer is smaller than the activity of the bump. In this way, the semiconductor structure of the present invention is easy to be manufactured and the manufacture cost is also reduced.

Abstract: An integrated circuit wafer dicing method is provided. The method includes forming a plurality of integrated circuits and a plurality of test-keys on a wafer substrate, wherein the plurality of test-keys are disposed between the adjacent integrated circuits; forming a patterned protective film on the wafer to cover the plurality of integrated circuits and expose the plurality of test-keys; etching the plurality of test-keys by using the patterned protective film as a mask; and dicing an area between the plurality of integrated circuits to form a plurality of discrete integrated circuit dies.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.

Abstract: A die structure and a die connecting method using the same are provided. The die structure includes a die and a bump structure. The bump structure includes a body and a solder layer. The body is disposed on the die. The solder layer is disposed on the body. The method includes providing a die structure mentioned above, providing a circuit board mentioned above, and soldering the solder layer of the die structure with the tine layer on the copper block of the circuit board. In different embodiments, a tin layer is omitted from the circuit board, wherein the solder layer of the die structure is directly soldered onto the surface of the copper block.

Abstract: An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a chip body and at least one bump. The chip body has at least one conducting area on its surface. The bump is formed on the conducting area of the chip body. The bump includes a plurality of protrusions and at least one conducting material. The protrusions protrude out of the conducting area and are spaced apart from each other. The conducting material covers the protrusions and electrically connects the conducting area. The method includes: (A) providing a chip body having a conducting area on its surface; (B) forming a plurality of protrusions on the chip body, wherein the protrusions protrude out of the conducting area and are spaced apart from each other; and (C) forming at least one conducting material, wherein the conducting material covers the protrusions and electrically connects the conducting area.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer.

Abstract: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer.

Abstract: The invention provides a semiconductor chip comprising a semiconductor substrate comprising a MOS device, an interconnecting structure over said semiconductor substrate, and a metal bump over said MOS device, wherein said metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Abstract: A method of metal sputtering, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer comprised of: a) a material etchable in a metal barrier layer etch process; or b) an insulating or non-conductive material. A wafer having two or more wafer conductive structures is placed upon the seasoning layer coated wafer holder. The wafer is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. A metal barrier layer is formed over the wafer. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of the metal barrier layer.