Abstract: An optoelectronic device includes a first substrate, a second substrate, a photonic integrated circuit, and a laser diode. The second substrate is over the first substrate. The photonic integrated circuit is disposed on the first substrate and includes a first waveguide channel, a second waveguide channel, and a patterned structure. The first waveguide channel and the second waveguide channel are coupled to the patterned structure. The laser diode is disposed on the second substrate and configured to emit a light beam toward the patterned structure.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.

Abstract: A frequency reconfigurable phased array system comprises a signal generator outputting a power signal with an adjustable frequency, a plurality of radio frequency (RF) modules receiving the power signal, a control module generating excitation mode parameter sets and material processing event sets, a first database storing the excitation mode parameter sets, and a second database storing the material processing event sets. The control module generates a material processing schedule by selecting one of the material processing event sets based on a material recipe, an average power, and a total time of a material, and controls a signal frequency of the signal generator according to the material processing schedule and the excitation mode parameter sets, and a RF phase and a RF power of each of the RF modules, to have the RF modules generating a power signal.

Abstract: A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

Abstract: A multi-layer display module includes a first display panel, and a second display panel. Dimension of long side of the first display panel is D1, and the first display panel has first pixel resolution P1. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space d between the first display panel and the second display panel. Dimension of the long side of the second display panel is D2, and the second display panel has the second pixel resolution P2. Transmittance of the second display panel is T2. The multi-layer display module complies with T2>40%, P1?P2, and D ? 2 * T ? 2 ? d ? D ? 2 ? "\[LeftBracketingBar]" P ? 1 - P ? 2 ? "\[RightBracketingBar]" * P ? 2 .

Abstract: A curable composition includes an epoxy monomer component and an aniline-based hardener. The epoxy monomer component is a first component formed from a first epoxy monomer represented by Formula (I), or a second component including the first epoxy monomer represented by Formula (I) and a second epoxy monomer different from the first epoxy monomer represented by Formula (I), wherein each of the substituents in Formula (I) is given the definitions as set forth in the Specification and Claims. Based on 100 wt % of the epoxy monomer component, an amount of the first epoxy monomer represented by Formula (I) is not smaller than 25 wt % and less than 100 wt % and an amount of the second epoxy monomer is greater than 0% and not greater than 75 wt %. A cured product formed from the curable composition, and a method for encapsulating a semiconductor device using the curable composition are also provided.

Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

Abstract: A display panel includes a substrate and a plurality of pixel structures disposed on the substrate. Each of the pixel structures includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is disposed on the substrate and configured to generate a first colored light. A light output surface of the first light-emitting element includes a combined region. The second light-emitting element is disposed on a part of the combined region and configured to generate a second colored light. The third light-emitting element is disposed on the other part of the combined region and configured to generate a third colored light.

Abstract: An optical member driving mechanism is provided. The optical member driving mechanism includes a first movable portion used for connecting an optical element, a fixed portion, a first driving assembly used for driving the first movable portion to rotate relative to the fixed portion, and a guiding assembly having a first intermediate element. The first movable portion is movable relative to the fixed portion. The guiding assembly is used for applying a first stabilized force to the first movable portion for making the first intermediate element be in contact with the first movable portion or the fixed portion. The first movable portion is rotatable relative to the fixed portion.

Abstract: A thin film transistor includes a stack of an active layer, a gate dielectric, and a gate electrode in a forward or in a reverse order. The active layer includes a compound semiconductor material containing oxygen, at least one acceptor-type element selected from Ga and W, and at least one heavy post-transition metal element selected from In and Sn. An atomic percentage of the at least one heavy post-transition metal element at a first surface portion of the active layer that contacts the gate dielectric is higher than an atomic percentage of the at least one heavy post-transition metal element at a second surface portion of the active layer located on an opposite side of the gate dielectric. The front channel current may be increased, and the back channel leakage current may be decreased.

Abstract: An LED package structure includes three LED dies and a black sealant layer. Each of the LED dies is provided with a bottom surface, a top surface, and a peripheral wall. The bottom surface and the top surface are opposite to each other, and the peripheral wall is connected to the top surface and the bottom surface. The black sealant layer is coated among the three LED dies and coats the peripheral wall of each of the LED dies. The black sealant layer is provided with a joint surface. The joint surface is coplanar with the bottom surface of each of the LED dies. The black sealant layer does not cover the top surface of each of the LED dies. Also provided is an LED display apparatus which has a better visual taste.

Abstract: A phase-change temperature regulating system and an electronic device testing apparatus and method are described. In an embodiment, the system uses a temperature regulating fluid chamber containing a temperature regulating fluid to allow the temperature regulating fluid to cover at least a part of at least one surface of an electronic component. When a temperature of the electronic component reaches a boiling point of the temperature regulating fluid, the temperature regulating fluid becomes steam through a phase change to transfer heat energy outward from the electronic component, and condenses on an inner surface of the fluid chamber to further transfer heat energy of the steam to a temperature-regulating apparatus. The condensed temperature regulating fluid flows back to the temperature regulating fluid, thereby continuously circulating.

Abstract: A power supply includes a power adapter unit and a plug unit. The power adapter unit includes a housing with an engaging base formed over bottom surface of the housing, a power conversion module installed in the housing, two electric contact pins in the engaging base electric connecting with the power conversion module, a locking member adjacent to the engaging base. The plug unit is slidably engaged with the engaging base including two plug pins and each of the plug pins electrically connected to a metal contact located at inner side of the plug unit, a locking matching member to interact with the locking member for allowing the plug unit lock or unlock from the engaging base. The plug unit is interchangeable with the power adapter unit. The metal contacts and the plug pins provide additional interlock interaction when the plug unit is slidably engaged with the power adapter unit.

Abstract: A multi-layer display module includes a first display panel, and a second display panel. The second display panel is located on one side of the first display panel and overlapped with the first display panel. There is a space between the first display panel and the second display panel. Transmittance of the second display panel is T2, luminance of the first display panel is L1, and luminance of the second display panel is L2. The multi-layer display module complies with T ? 2 > 40 ? % and 0.8 ? L ? 1 L ? 2 * ( 1 - T ? 2 ) .

Abstract: An inspection system with a thermal interface, and an electronic component inspection device and method are provided. First, a temperature regulator contacts an electronic component to be tested, where there is a thermal interface between the temperature regulator and the electronic component to be tested, and the electronic component to be tested includes a plurality of temperature sensing units. Then, the temperature regulator heats or cools the electronic component to be tested to a specific temperature, and the plurality of temperature sensing units of the electronic component to be tested detect temperatures at locations of the temperature sensing units. In this way, a contact condition between the temperature regulator and the electronic component to be tested, and quality or an aging status of the thermal interface can be determined.

Abstract: In an embodiment, a method includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure including doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.

Abstract: An offset overlap type of a modulated ferromagnetic pole piece ring and a manufacturing method thereof are provided. The modulated ferromagnetic pole piece ring comprises a plurality of ring pieces overlapped with each other. At least one ring piece comprises a plurality of main ribs, a plurality of inner ribs, and a plurality of outer ribs. The main ribs are arranged in a circular manner with intervals in between, and a plurality of first gaps and a plurality of second gaps are formed alternately between the main ribs, wherein the inner ribs are respectively located in the first gaps, and the outer ribs are respectively located in the second gaps.

Abstract: The present application discloses an implanting system. The implanting system includes an etch module executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second implanting recipe taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Abstract: A circuit layout checking method includes: determining whether there is only a first layout pattern and/or a second layout pattern corresponding to a filler cell or a second gate array cell exist in a region extending outward from the first layout pattern corresponding to a first gate array cell; determining whether a first pattern corresponding to an electrical connection layer in the first layout pattern is enclosed by a second pattern corresponding to a metal layer in the first layout pattern and whether each spacing between all boundaries of the first pattern and those of the second pattern is not less than a predetermined distance; and if there is only the first and/or second layout patterns in the first region and if the first pattern is enclosed by the second pattern and each spacing is not less than the predetermined distance, generating data indicating layout design of an integrated circuit.