Abstract: A method for managing passwords for a BIOS and a BMC is implemented by a computer including a processor, a BMC, a platform controller hub (PCH), a first non-volatile memory and a second non-volatile memory. The BMC stores a BMC password, the first non-volatile memory stores a BIOS password, and the second non-volatile memory stores a first string and a second string. The method includes steps of: upon receiving a command for changing the BIOS password, the processor changing the BIOS password via the PCH according to the command; the processor changing the second string via the PCH to be the same as the BIOS password; the processor rebooting the computer; the BMC changing the first string via the PCH to be the same as the second string; and the BMC changing the BMC password to be the same as the first string.

Abstract: The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap.

Abstract: An optoelectronic device includes a first substrate, a second substrate, a photonic integrated circuit, and a laser diode. The second substrate is over the first substrate. The photonic integrated circuit is disposed on the first substrate and includes a first waveguide channel, a second waveguide channel, and a patterned structure. The first waveguide channel and the second waveguide channel are coupled to the patterned structure. The laser diode is disposed on the second substrate and configured to emit a light beam toward the patterned structure.

Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.

Abstract: A phase-change temperature regulating system and an electronic device testing apparatus and method are described. In an embodiment, the system uses a temperature regulating fluid chamber containing a temperature regulating fluid to allow the temperature regulating fluid to cover at least a part of at least one surface of an electronic component. When a temperature of the electronic component reaches a boiling point of the temperature regulating fluid, the temperature regulating fluid becomes steam through a phase change to transfer heat energy outward from the electronic component, and condenses on an inner surface of the fluid chamber to further transfer heat energy of the steam to a temperature-regulating apparatus. The condensed temperature regulating fluid flows back to the temperature regulating fluid, thereby continuously circulating.

Abstract: A power supply includes a power adapter unit and a plug unit. The power adapter unit includes a housing with an engaging base formed over bottom surface of the housing, a power conversion module installed in the housing, two electric contact pins in the engaging base electric connecting with the power conversion module, a locking member adjacent to the engaging base. The plug unit is slidably engaged with the engaging base including two plug pins and each of the plug pins electrically connected to a metal contact located at inner side of the plug unit, a locking matching member to interact with the locking member for allowing the plug unit lock or unlock from the engaging base. The plug unit is interchangeable with the power adapter unit. The metal contacts and the plug pins provide additional interlock interaction when the plug unit is slidably engaged with the power adapter unit.

Abstract: An inspection system with a thermal interface, and an electronic component inspection device and method are provided. First, a temperature regulator contacts an electronic component to be tested, where there is a thermal interface between the temperature regulator and the electronic component to be tested, and the electronic component to be tested includes a plurality of temperature sensing units. Then, the temperature regulator heats or cools the electronic component to be tested to a specific temperature, and the plurality of temperature sensing units of the electronic component to be tested detect temperatures at locations of the temperature sensing units. In this way, a contact condition between the temperature regulator and the electronic component to be tested, and quality or an aging status of the thermal interface can be determined.

Abstract: An offset overlap type of a modulated ferromagnetic pole piece ring and a manufacturing method thereof are provided. The modulated ferromagnetic pole piece ring comprises a plurality of ring pieces overlapped with each other. At least one ring piece comprises a plurality of main ribs, a plurality of inner ribs, and a plurality of outer ribs. The main ribs are arranged in a circular manner with intervals in between, and a plurality of first gaps and a plurality of second gaps are formed alternately between the main ribs, wherein the inner ribs are respectively located in the first gaps, and the outer ribs are respectively located in the second gaps.

Abstract: The present application discloses an implanting system. The implanting system includes an etch module executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second implanting recipe taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Abstract: A circuit layout checking method includes: determining whether there is only a first layout pattern and/or a second layout pattern corresponding to a filler cell or a second gate array cell exist in a region extending outward from the first layout pattern corresponding to a first gate array cell; determining whether a first pattern corresponding to an electrical connection layer in the first layout pattern is enclosed by a second pattern corresponding to a metal layer in the first layout pattern and whether each spacing between all boundaries of the first pattern and those of the second pattern is not less than a predetermined distance; and if there is only the first and/or second layout patterns in the first region and if the first pattern is enclosed by the second pattern and each spacing is not less than the predetermined distance, generating data indicating layout design of an integrated circuit.

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.

Abstract: The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate.

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Abstract: A semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap, and a second portion of the dielectric layer between the third composite conductive feature and the fourth composite conductive feature is in direct contact with the semiconductor substrate.

Abstract: The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap.

Abstract: The present application provides a memory device having a bit line (BL) with a stepped profile. The memory device includes a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system uses a cooling fluid supply module for the cooling of the pogo pin, and the cooling fluid may be either a coolant or a cooling gas. When an electronic device is accommodated in the chip socket, the cooling fluid supply module supplies a cooling fluid into the chip socket through the cooling fluid supply channel and the inlet, and the cooling fluid passes through the pogo pins and then flows into the cooling fluid discharge channel through the outlet. In the present invention, the cooling fluid is mainly used to cool not only the pogo pins in the chip socket but also the bottom surface of the electronic device and the solder ball contacts on the bottom surface.

Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.