Abstract: The present disclosure provides a semiconductor device with a composite conductive feature and an air gap and a method for preparing the semiconductor device. The semiconductor device includes a first composite conductive feature and a second composite conductive feature disposed over a pattern-dense region of a semiconductor substrate. The semiconductor device also includes a third composite conductive feature and a fourth composite conductive feature disposed over a pattern-loose region of the semiconductor substrate. The semiconductor device further includes a dielectric layer disposed over the pattern-dense region and the pattern-loose region of the semiconductor substrate. A first portion of the dielectric layer between the first composite conductive feature and the second composite conductive feature is separated from the semiconductor substrate by an air gap.

Abstract: The present application provides a memory device having a bit line (BL) with a stepped profile. The memory device includes a semiconductor substrate including a first surface; and a bit line disposed on the first surface of the semiconductor substrate, wherein the bit line includes a first dielectric layer, a conductive layer disposed over the first dielectric layer, a second dielectric layer disposed over the conductive layer, and a spacer surrounding the first dielectric layer, the conductive layer and the second dielectric layer, wherein the second dielectric layer includes a first portion surrounded by the spacer, and a second portion disposed over the first portion and exposed through the spacer, wherein a first width of the first portion is substantially greater than a second width of the second portion.

Abstract: A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system uses a cooling fluid supply module for the cooling of the pogo pin, and the cooling fluid may be either a coolant or a cooling gas. When an electronic device is accommodated in the chip socket, the cooling fluid supply module supplies a cooling fluid into the chip socket through the cooling fluid supply channel and the inlet, and the cooling fluid passes through the pogo pins and then flows into the cooling fluid discharge channel through the outlet. In the present invention, the cooling fluid is mainly used to cool not only the pogo pins in the chip socket but also the bottom surface of the electronic device and the solder ball contacts on the bottom surface.

Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.

Abstract: An encoder module adapted for a robotic arm is provided and includes a bracket, a bearing embedded in the bracket, an adaptor ring embedded in the bearing, a circuit board fixed on the bracket and an encoder plate. The bracket includes a ring-shaped structure. The adaptor ring includes a ring-shaped flange portion and a protruding portion. The protruding portion is located adjacent to an inner periphery of the ring-shaped flange portion and protrudes from the ring-shaped flange portion. An outer periphery and an inner periphery of the bearing engage with an inner periphery of the ring-shaped structure and an outer periphery of the protruding portion respectively. The circuit board includes a detector. The encoder plate is fixed on the ring-shaped flange portion and located at a position corresponding to the detector and between the detector and the adaptor ring. The encoder module has less accumulated error and improved accuracy.

Abstract: A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Abstract: A deposition method includes executing a first deposition recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first deposition recipe to a second deposition recipe when the first set of data is not within a predetermined range. The second deposition recipe is generated taking into consideration at least one of a deposition rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an etching recipe of the first wafer, and an implanting recipe of the first wafer. The second deposition recipe is configured to be applied on a second wafer to be processed after the first wafer.

Abstract: The present application discloses an etching system. The etching system includes an etch module executing a first etching recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first etching recipe to a second etching recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second etching recipe taking into consideration at least one of an etching rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Abstract: The present application discloses a deposition system. The deposition system includes a deposition module executing a first deposition recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first deposition recipe to a second deposition recipe when the first set of data is not within a predetermined range.

Abstract: An etching method includes executing a first etching recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first etching recipe to a second etching recipe when the first set of data is not within a predetermined range. The second etching recipe is generated taking into consideration at least one of an etching rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an implanting recipe of the first wafer, and a deposition recipe of the first wafer. The second etching recipe is configured to be applied on a second wafer to be processed after the first wafer.

Abstract: An implanting method includes executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; collecting the second wafer state of the first wafer to generate a first set of data; and analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The second implanting recipe is generated taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, a tilt angle of the second wafer, an etching recipe of the first wafer, and a deposition recipe of the first wafer. The second implanting recipe is configured to be applied on a second wafer to be processed after the first wafer.

Abstract: The present application discloses an implanting system. The implanting system includes an etch module executing a first implanting recipe on a first wafer to turn a first wafer state of the first wafer to a second wafer state; a first measurement module collecting the second wafer state of the first wafer to generate a first set of data; and an artificial intelligence module coupled to the first measurement module and the etch module, analyzing the first set of data and update the first implanting recipe to a second implanting recipe when the first set of data is not within a predetermined range. The artificial intelligence module is configured for generating the second implanting recipe taking into consideration at least one of an implanting rate of the second wafer, a rate of rotation of the second wafer, and a tilt angle of the second wafer.

Abstract: A liquid cooling system, a liquid cooling method, and an electronic device-testing apparatus having the system are disclosed. When an electronic device is accommodated in a chip slot of a test socket, a cooling liquid supply device supplies a cooling liquid to the chip slot through a fluid inlet portion, and the cooling liquid at least flows over parts of the upper and lower surfaces of the electronic device and then flows out from a fluid outlet portion. The chip slot of the test socket serves as the flow space for the cooling liquid so that the cooling liquid can flow over the upper and lower surfaces of the electronic device, and the electronic device can be immersed in the continuously flowing cooling liquid. The flowing cooling liquid can also take away foreign matter, avoiding the influence of the foreign matter on the test.

Abstract: The present invention relates to a temperature control system and a temperature control method for an electronic device-testing apparatus. The temperature control system mainly includes a test socket, a temperature-controlling fluid supply device and a temperature-controlling fluid recovery device. A temperature-controlling fluid is supplied to a chip slot of the test socket by the temperature-controlling fluid supply device and drawn from the chip slot by the temperature-controlling fluid recovery device. In the present invention, the temperature-controlling fluid is forced to flow through the chip slot loaded with an electronic device so as to forcibly exchange heat with the electronic device and components in the chip slot, thereby achieving the constant temperature test. After the test is completed, the temperature-controlling fluid can be effectively recovered so that the contamination of the electronic device or the testing apparatus can be avoided.

Abstract: An inner circulation ball screw includes a screw shaft, a nut, and a return member. The nut is disposed on the screw shaft to form a load path with the screw shaft. The return member is disposed in an accessory slot of the nut to form a non-load path connected with the load path to form a circulation path for circulation of balls. The return member has a ball-discharging channel provided with one end connected with an ineffective thread section of the nut and the other end communicating with a ball-discharging hole of the nut. Therefore, the balls are allowed to move to the outside of the nut through the ball-discharging channel and the ball-discharging hole for preventing the balls from being stuck in the ineffective thread section, thereby solving the problems of high resistance and damaging to related accessories.

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.

Abstract: A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Abstract: A method of estimating a d-q axis inductance of a permanent magnet synchronous motor includes the following steps. First, building an equivalent motor control block through enabling two of the three phases, and disabling the remaining one of the three phases, and locking a rotor. Afterward, incorporating a back EMF observer into a DC motor control block, and making the DC motor control block correspond to the back EMF observer by commanding an angular speed of the DC motor control block to be zero. Afterward, introducing the equivalent motor control block into the DC motor control block, and using the back EMF observer to estimate the back EMF, and repeating above steps taking turns to disable one phase so as to obtain three sets of motor inductances respectively. Finally, estimating the d-q axis inductance by introducing the three sets of equivalent motor inductances into an inductance relational equation.