Patents by Inventor Ching Wang

Ching Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250221310
    Abstract: A liquid cooling system includes a thermoelectric cooler (TEC) between a radiator plate and a radiator, and a thermoelectric generator (TEG) at a location where the TEG is driven by heat from a chip package. The chip package is cooled by a cold plate of the liquid cooling system and the TEC is controlled by the TEG. The TEG may be between the chip package and the cold plate or elsewhere in or adjacent to the chip package. The TEG may control the TEC through a relay. The TEG automatically activates the TEC when the chip package is under peak load.
    Type: Application
    Filed: April 9, 2024
    Publication date: July 3, 2025
    Inventors: Chien-Chang Wang, Kuan-Min Wang, Ching Wang, Kuo-Chin Chang, Kathy Wei Yan, Jun He
  • Publication number: 20250210458
    Abstract: A package structure includes a high-power package attached to a substrate; a first low-power package attached to the substrate; a first heat dissipation device attached to the first low-power package; a liquid cooling system attached to the high-power package; and a thermoelectric system sandwiched between the high-power package and the liquid cooling system, wherein the thermoelectric system is electrically connected to the first heat dissipation device, wherein the thermoelectric system provides the first heat dissipation device with electrical power during operation of the high-power package.
    Type: Application
    Filed: March 11, 2024
    Publication date: June 26, 2025
    Inventors: Chien-Chang Wang, Kuan-Min Wang, Ching Wang, Kuo-Chin Chang, Kathy Wei Yan, Jun He
  • Publication number: 20250210420
    Abstract: An integrated circuit package and the method of forming the same are provided. An integrated circuit package may include a first die having a first substrate over a package substrate and a lid. A first channel may extend through the first substrate from a first sidewall of the first die to a second sidewall of the first die. The lid may include a top portion over the first die and a first bottom portion extending along the first sidewall of the first die. The first bottom portion may include a second channel connected to the first channel.
    Type: Application
    Filed: April 16, 2024
    Publication date: June 26, 2025
    Inventors: Bang Li Wu, Ching Wang, Chien-Chang Wang, Kuo-Chin Chang, Kathy Wei Yan, Jun He
  • Publication number: 20250197373
    Abstract: A small molecule compound or salt thereof or solvates of them is provided, wherein the small molecule compound comprises a compound represented by Formula (I) as shown below:
    Type: Application
    Filed: November 29, 2024
    Publication date: June 19, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wan-Ru CHEN, Chih-Hung CHEN, Yow-Lone CHANG, Shu-Feng CHEN, Hsiang-Ching WANG, Shu-Ling WANG, Yen-Ju LIN, Ming-Hsi WU
  • Publication number: 20250157894
    Abstract: A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second FET, an integrated circuit (IC), a plurality of bond wires, and a molding encapsulation. The lead frame comprises a first die paddle and a second die paddle. The first FET is flipped and attached to the first die paddle. The second FET is flipped and attached to the second die paddle. A method comprises the steps of providing a lead frame comprising a first die paddle and a second die paddle; applying a first adhesive layer; mounting a first FET and a second FET; applying a second adhesive layer; mounting an IC; applying bonding wires; forming a molding encapsulation; and applying a singulation process so as to form a plurality of semiconductor packages.
    Type: Application
    Filed: June 28, 2024
    Publication date: May 15, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Jian Yin, Long-Ching Wang, Sitthipong Angkititrakul, Xiaobin Wang, Bo Chen
  • Publication number: 20250151226
    Abstract: A heat dissipation device and a computer device are disclosed. The heat dissipation device includes a case and a fan module. The case includes a first wall, a second wall and an accommodation cavity. The accommodation cavity is located between the first wall and the second wall in a first direction. The first wall includes a first through hole. The second wall includes a second through hole. The first through hole is connected to the accommodation cavity, the second through hole is connected to the accommodation cavity. The fan module is mounted in the accommodation cavity. The fan module includes a bracket assembly and a plurality of fans. The bracket assembly is detachably connected to the plurality of fans and the case.
    Type: Application
    Filed: November 6, 2024
    Publication date: May 8, 2025
    Inventors: PAO-CHING WANG, WEN-CHEN WANG
  • Publication number: 20250149392
    Abstract: A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.
    Type: Application
    Filed: December 26, 2023
    Publication date: May 8, 2025
    Applicant: Unimicron Technology Corp.
    Inventors: Chia Ching Wang, Chien-Chou Chen, Hsuan Ming Hsu, Ho-Shing Lee, Yunn-Tzu Yu, Yao Yu Chiang, Po-Wei Chen, Wei-Ti Lin, Wen Chi Chang
  • Publication number: 20250151357
    Abstract: Semiconductor structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin rising from the substrate, an isolation feature disposed over the substrate and between the first base fin and the second base fin, a first bottom epitaxial feature over the first base fin, a second bottom epitaxial feature over the second base fin, an isolation layer on the first bottom epitaxial feature, a first source/drain feature over the isolation layer, a second source/drain feature disposed over and in contact with the second bottom epitaxial feature, a contact etch stop layer (CESL) over the first source/drain feature and the isolation feature, a first interlayer dielectric (ILD) layer over the CESL, and a second ILD layer over and in direct contact with the second source/drain feature.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Inventors: Bo-Yu Lai, Chung-I Yang, Wei-Yang Lee, Chih-Ching Wang
  • Publication number: 20250129101
    Abstract: Disclosed is a compound represented by the following formula (I), or a pharmaceutically acceptable salt thereof: wherein R1, R2, R3, R4, R5 and R6 are defined in the specification. Also disclosed is a pharmaceutical composition comprising the same and a method for treating a cancer using the same.
    Type: Application
    Filed: October 18, 2024
    Publication date: April 24, 2025
    Inventors: Hui-Ching WANG, Hsing-Pang HSIEH, Ching-Chuan KUO, Yuh-Ju SUN, Yuan-Shao PAO, Kuan-Ju LIAO, Ya-Chia SHIAU
  • Patent number: 12283215
    Abstract: A display device including a display panel and a driving circuit is provided. The display panel is configured to display an image frame. The driving circuit is coupled to the display panel. The driving circuit is configured to output a gate signal to drive the display panel to display the image frame during a driving period. The driving period includes a first period, a second period, and a third period. The gate signal has a first voltage level during the first period and a second voltage level during the second period. The second voltage level is greater than the first voltage level.
    Type: Grant
    Filed: February 19, 2024
    Date of Patent: April 22, 2025
    Assignee: E Ink Holdings Inc.
    Inventors: Wen-Chuan Wang, Ian French, Kuang-Heng Liang, Chih-Ching Wang
  • Publication number: 20250118638
    Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Jian Yin, Lin Chen, Ziwei Yu, Xiaobin Wang, Zhiqiang Niu, Kuan-Hung Li
  • Publication number: 20250119960
    Abstract: A hotspot communication stabilization system includes a hotspot communication stabilizer. The hotspot communication stabilizer includes a connected device address search unit and a comparator. The connected device address search unit serves to obtain at least one connection address from a communication host device at regular or irregular intervals. The connection address is an address of a peripheral communication device connected to the communication host device and is stored in a connection address table. The comparator serves to determine whether there is a missing address in the connection address table at a current time by comparing two connection addresses of the peripheral communication device at two adjacent times. The missing address is sent to the communication host device and the communication host device re-establishes a hotspot signal connection to the missing address corresponded to a corresponding peripheral communication device.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: YAO CHING WANG, YI CHIEH CHEN, YU NING LAN
  • Publication number: 20250112132
    Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises a top plate, a plurality of drain pads, a plurality of slanted sections, a gate pad, and a plurality of source pads. The top plate of the lead frame comprises a thicker region and a thinner region. Each slanted section of the plurality of slanted sections connects a respective drain pad of the plurality of drain pads to the top plate. A respective side surface of each drain pad of the plurality of drain pads is exposed from a side surface of the molding encapsulation. A respective bottom surface of each drain pad of the plurality of drain pads is exposed from a bottom surface of the molding encapsulation. A top surface of the thicker region is exposed from a top surface of the molding encapsulation.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Zhiqiang Niu, Xiao Zhang, Long-Ching Wang, Guobing Shen, Yan Xun Xue
  • Publication number: 20250104364
    Abstract: A method for displaying a virtual image to a user is implemented by a computing device. The method includes to first obtain an initial position of the user, and define a reference point at the initial position of the user. Then, the computing device obtains a user position of the user, and determines whether a distance between a position of the reference point and the user position is greater than a threshold. If the distance is greater than the threshold, the computing device moves the position of the reference point to a reference position that is at most the threshold away from the user position. Finally, the computing device obtains a display position as a relative position based on the position of the reference point, and displays the virtual image at the display position.
    Type: Application
    Filed: July 9, 2024
    Publication date: March 27, 2025
    Inventors: Tsung-Hsiu YU, Chun-Ching WANG, Shih-Wei CHEN
  • Patent number: 12261101
    Abstract: A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie bar, the second tie bar, the third tie bar, and the fourth tie bar is not plated with the metal. A method for fabricating a semiconductor package includes the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, applying a trimming process, applying a plating process, and applying a singulation process.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 25, 2025
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Xiaoguang Zeng
  • Publication number: 20250096081
    Abstract: A semiconductor package comprising a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, an interposer, an integrated circuit (IC) controller, and a molding encapsulation. A method, for fabricating a semiconductor package, comprises the steps of: providing a lead frame; attaching a low side FET and a high side FET; mounting a metal clip; attaching an interposer; mounting an IC controller, forming a molding encapsulation; and applying a singulation process.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 20, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Madhur Bobde, Yan Xun Xue, Long-Ching Wang, Jian Yin, Sitthipong Angkititrakul
  • Publication number: 20250089333
    Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming an epitaxial stack of channel layers and sacrificial layers on a semiconductor substrate, patterning the epitaxial stack to form a first fin-shape structure in a first region and a second fin-shape structure in a second region, etching the first fin-shape structure to form a first source/drain recess, etching the second fin-shape structure to form a second source/drain recess, forming first inner spacers in the first region, forming second inner spacers in the second region, laterally recessing the second inner spacers, forming a first source/drain feature in the first source/drain recess, and forming a second source/drain feature in the second source/drain recess. After the laterally recessing of the second inner spacers, the second inner spacers have a thickness less than the first inner spacers.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 13, 2025
    Inventors: Hung-Ju Chou, Wei-Yang Lee, Chih-Ching Wang, Yuan-Ching Peng
  • Patent number: 12243808
    Abstract: A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 ?m to 35 ?m. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: March 4, 2025
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Lin Lv, Shuhua Zhou, Long-Ching Wang, Jun Lu
  • Publication number: 20250069973
    Abstract: A chip scale semiconductor package comprises a silicon layer, a back side metal layer, and a plurality of front side pads. Each of the plurality of front side pads comprises a respective copper member and a respective solder member. A method comprises the steps of: providing a wafer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Zhiqiang Niu, Lin Lv
  • Publication number: 20250070069
    Abstract: A semiconductor package comprises a semiconductor substrate, a plurality of contact pads, a plurality of metal bumps, a metal layer, and a molding encapsulation. A thickness of the semiconductor substrate is less than 35 microns. A first method comprises the steps of providing a device wafer; attaching a first carrier; applying a thinning process; forming a metal layer; applying a first tape; removing the first carrier; applying a first singulation process; removing the first tape; attaching a second carrier; forming a molding encapsulation; removing the second carrier; forming a plurality of metal bumps; applying a second tape; and applying a singulation process and removing the second tape. A second method comprises the steps of providing a device wafer; attaching a carrier; applying a thinning process; forming a metal layer; forming a molding encapsulation; removing the carrier; forming a plurality of metal bumps; and applying a singulation process.
    Type: Application
    Filed: July 25, 2024
    Publication date: February 27, 2025
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Lin Lv, Zhen Yang, Shuhua Zhou, Long-Ching Wang