Abstract: A heat dissipation device and a computer device are disclosed. The heat dissipation device includes a case and a fan module. The case includes a first wall, a second wall and an accommodation cavity. The accommodation cavity is located between the first wall and the second wall in a first direction. The first wall includes a first through hole. The second wall includes a second through hole. The first through hole is connected to the accommodation cavity, the second through hole is connected to the accommodation cavity. The fan module is mounted in the accommodation cavity. The fan module includes a bracket assembly and a plurality of fans. The bracket assembly is detachably connected to the plurality of fans and the case.

Abstract: A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.

Abstract: Semiconductor structures and methods for forming the same are provided. A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin rising from the substrate, an isolation feature disposed over the substrate and between the first base fin and the second base fin, a first bottom epitaxial feature over the first base fin, a second bottom epitaxial feature over the second base fin, an isolation layer on the first bottom epitaxial feature, a first source/drain feature over the isolation layer, a second source/drain feature disposed over and in contact with the second bottom epitaxial feature, a contact etch stop layer (CESL) over the first source/drain feature and the isolation feature, a first interlayer dielectric (ILD) layer over the CESL, and a second ILD layer over and in direct contact with the second source/drain feature.

Abstract: Disclosed is a compound represented by the following formula (I), or a pharmaceutically acceptable salt thereof: wherein R1, R2, R3, R4, R5 and R6 are defined in the specification. Also disclosed is a pharmaceutical composition comprising the same and a method for treating a cancer using the same.

Abstract: A display device including a display panel and a driving circuit is provided. The display panel is configured to display an image frame. The driving circuit is coupled to the display panel. The driving circuit is configured to output a gate signal to drive the display panel to display the image frame during a driving period. The driving period includes a first period, a second period, and a third period. The gate signal has a first voltage level during the first period and a second voltage level during the second period. The second voltage level is greater than the first voltage level.

Abstract: A semiconductor package comprises a first device and a second device. The structure of the first semiconductor device is similar to that of the second semiconductor device. The first semiconductor device comprises a lead frame strip, a first plurality of field effect transistors (FETs), a first plurality of clips, a second plurality of FETs, a second plurality of clips, and a first molding encapsulation. A method is applied to fabricate a plurality of semiconductor packages. The method comprises the steps of providing a lead frame strip, attaching a first plurality of FETs, attaching a first plurality of clips, attaching a second plurality of FETs, attaching a second plurality of clips, and forming a molding encapsulation.

Abstract: A hotspot communication stabilization system includes a hotspot communication stabilizer. The hotspot communication stabilizer includes a connected device address search unit and a comparator. The connected device address search unit serves to obtain at least one connection address from a communication host device at regular or irregular intervals. The connection address is an address of a peripheral communication device connected to the communication host device and is stored in a connection address table. The comparator serves to determine whether there is a missing address in the connection address table at a current time by comparing two connection addresses of the peripheral communication device at two adjacent times. The missing address is sent to the communication host device and the communication host device re-establishes a hotspot signal connection to the missing address corresponded to a corresponding peripheral communication device.

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises a top plate, a plurality of drain pads, a plurality of slanted sections, a gate pad, and a plurality of source pads. The top plate of the lead frame comprises a thicker region and a thinner region. Each slanted section of the plurality of slanted sections connects a respective drain pad of the plurality of drain pads to the top plate. A respective side surface of each drain pad of the plurality of drain pads is exposed from a side surface of the molding encapsulation. A respective bottom surface of each drain pad of the plurality of drain pads is exposed from a bottom surface of the molding encapsulation. A top surface of the thicker region is exposed from a top surface of the molding encapsulation.

Abstract: A method for displaying a virtual image to a user is implemented by a computing device. The method includes to first obtain an initial position of the user, and define a reference point at the initial position of the user. Then, the computing device obtains a user position of the user, and determines whether a distance between a position of the reference point and the user position is greater than a threshold. If the distance is greater than the threshold, the computing device moves the position of the reference point to a reference position that is at most the threshold away from the user position. Finally, the computing device obtains a display position as a relative position based on the position of the reference point, and displays the virtual image at the display position.

Abstract: A semiconductor package includes a lead frame, a chip, and a molding encapsulation. The lead frame comprises a die paddle, a first plurality of leads, additional one or more leads, a second plurality of leads, a first tie bar, a second tie bar, a third tie bar, and a fourth tie bar. A respective end surface of each lead of the first plurality of leads, the additional one or more leads, and the second plurality of leads is plated with a metal. A respective end surface of the first tie bar, the second tie bar, the third tie bar, and the fourth tie bar is not plated with the metal. A method for fabricating a semiconductor package includes the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, applying a trimming process, applying a plating process, and applying a singulation process.

Abstract: A semiconductor package comprising a lead frame, a low side field-effect transistor (FET), a high side FET, a metal clip, an interposer, an integrated circuit (IC) controller, and a molding encapsulation. A method, for fabricating a semiconductor package, comprises the steps of: providing a lead frame; attaching a low side FET and a high side FET; mounting a metal clip; attaching an interposer; mounting an IC controller, forming a molding encapsulation; and applying a singulation process.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming an epitaxial stack of channel layers and sacrificial layers on a semiconductor substrate, patterning the epitaxial stack to form a first fin-shape structure in a first region and a second fin-shape structure in a second region, etching the first fin-shape structure to form a first source/drain recess, etching the second fin-shape structure to form a second source/drain recess, forming first inner spacers in the first region, forming second inner spacers in the second region, laterally recessing the second inner spacers, forming a first source/drain feature in the first source/drain recess, and forming a second source/drain feature in the second source/drain recess. After the laterally recessing of the second inner spacers, the second inner spacers have a thickness less than the first inner spacers.

Abstract: A semiconductor device comprises a semiconductor substrate, a plurality of metal layers, an adhesive layer, a compound layer, and a plurality of contact pads. A thickness of the semiconductor substrate is in a range from 15 ?m to 35 ?m. A thickness of the compound layer is larger than the thickness of the semiconductor substrate. A coefficient of thermal expansion of the compound layer is less than or equal to 9 ppm/° C. A glass transition temperature of the compound layer is larger than 150° C. The plurality of metal layers comprises a first titanium layer, a first nickel layer, a silver layer, a second nickel layer, and a metallic layer. In a first example, the metallic layer is a second titanium layer. In a second example, the metallic layer is a Titanium Nitride (TiN) layer.

Abstract: A semiconductor package comprises a semiconductor substrate, a plurality of contact pads, a seed layer, a first thick metal layer, a second thick metal layer, and a coating metal layer. Direct attachment of the first thick metal layer and the second thick metal layer comprises bonded metal atoms. The first thick metal layer and the second thick metal layer are bonded by an SAB process. A method comprises the steps of providing an upper device portion, providing a lower carrier portion, applying an SAB process, applying a de-bonding process, applying a tape, applying a singulation process, and removing the tape.

Abstract: A chip scale semiconductor package comprises a silicon layer, a back side metal layer, and a plurality of front side pads. Each of the plurality of front side pads comprises a respective copper member and a respective solder member. A method comprises the steps of: providing a wafer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process.

Abstract: A semiconductor package comprises a semiconductor substrate, a plurality of contact pads, a plurality of metal bumps, a metal layer, and a molding encapsulation. A thickness of the semiconductor substrate is less than 35 microns. A first method comprises the steps of providing a device wafer; attaching a first carrier; applying a thinning process; forming a metal layer; applying a first tape; removing the first carrier; applying a first singulation process; removing the first tape; attaching a second carrier; forming a molding encapsulation; removing the second carrier; forming a plurality of metal bumps; applying a second tape; and applying a singulation process and removing the second tape. A second method comprises the steps of providing a device wafer; attaching a carrier; applying a thinning process; forming a metal layer; forming a molding encapsulation; removing the carrier; forming a plurality of metal bumps; and applying a singulation process.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: A multiple-reference-embedded comparator (MREC) circuit includes a tail current source circuit; an input transistor pair, coupled to the tail current source circuit, configured to receive differential input voltages and perform a first pre-amplification to generate first differential amplified voltages according to the differential input voltages; and a plurality of embedded reference (ER) branches, each coupled to the input transistor pair, each configured to perform a second pre-amplification to generate second differential amplified voltages according to the first differential amplified voltages, and to perform a discrete-time comparison to generate differential output voltages according to the second differential amplified voltages.

Abstract: A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Abstract: A method includes forming a first pull-up transistor and a first pass-gate transistor over a substrate at a first level height, the first pull-up and first pass-gate transistors being of a dual port static random access memory (SRAM) cell; forming a first pull-down transistor and a second pass-gate transistor of the dual port SRAM cell over the substrate at a second level height; forming a second pull-down transistor and a third pass-gate transistor of the dual port SRAM cell over the substrate at a third level height; forming a second pull-up transistor and a fourth pass-gate transistor of the dual port SRAM cell over the substrate at a fourth level height.