Abstract: An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.

Abstract: A method for providing service-related data includes: obtaining header information associated with a merchant based on registration information associated with the merchant, the registration information at least including a location of the merchant; based on product data associated with the merchandise, obtaining merchandise-related data associated with a merchandise provided by the merchant; obtaining content information based on the product data and the merchandise-related data; generating the service-related data using the header information and the content information; and transmitting the service-related data to a server as an entry of to-be-searched service-related data to enable the server to store the entry of to-be-searched service-related data in a data storage.

Abstract: A liquid cooling structure for a server with low-force quickseal joints to carry the coolant includes a first support, a first joint, a second support, a second joint, a first magnet, and a second magnet. The first support is set on the cabinet body. The second support is set on the server body. The first joint is set on the first support. The second joint is arranged on the second support and can be coupled with the first joint. The first magnet is set on first support. The second magnet is set on second support. The first magnet and second magnet with opposite magnetism attract each other to reduce the amount of force required for coupling the first joint and the second joint, and is labor-saving.

Abstract: An air-cooled carrier of heat-generating electronic components includes a frame, a plate, and baffles. The plate coupled to the frame divides airflow in the frame into two channels. Opposite sides of each channel along a first direction carry inlet and outlet. A pair of baffles is coupled to each channel, each baffle comprises a mounting part, an arc-shaped elastic part, and a blocking part. The mounting part is fixed to the frame and the arc-shaped elastic part. The blocking part is fixed to the arc-shaped elastic part and extends to middle of the airflow cavity in a second direction perpendicular to the first direction. In the absence of a mounted storage component, the elastic part bringing the blocking part to a first position and so blocking air flow from that outlet to that inlet.

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) stack and a capping layer on the MTJ stack. The MTJ stack includes a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer. The capping layer includes a metal under layer that is in direct contact with the free layer, an oxide capping layer on the metal under layer, and a metal protection layer on the oxide capping layer.

Abstract: The present invention relates to a scalable process for the purification of human cytomegalovirus particles from cell culture medium. In particular, the process involves a two step chromatography process starting with an anion exchange chromatography step followed by a polishing chromatography step selected from mixed mode chromatography or cation exchange chromatography.

Abstract: Disclosed herein is an improved system and methods implemented by the system for training a model that capable of identifying a hormone receptor status of a subject via the whole slide images (WSIs) of hematoxylin and eosin (H&E) stain of his/her biopsies. The method comprises steps of: (a) obtaining multiple WSIs having known hormone receptor information; (b) dividing each of the WSIs into a plurality of patches; (c) selecting and combining the patches that express the abnormal H&E stain into a combined image; and (d) training a plurality of combined images independently with the aid of the known hormone receptor information of the WSIs, thereby constructing the model. Also disclosed herein is a method for identifying a hormone receptor status of a subject by using the method and model implemented in the present system.

Abstract: A semiconductor package comprises two or more chips, a first molding layer, a second molding layer, a third molding layer, a fourth molding layer, a bottom redistribution layer (RDL), a middle RDL, and a top RDL. The two or more chips comprise a first chip and a second chip. The top RDL comprises a first copper plate and a second copper plate. A plurality of vias electrically connect the second copper plate to the second chip. A method comprises the steps of preparing two or more chips; forming a chip-level molding layer; forming a middle RDL; forming a lower-level molding layer; forming a bottom RDL; forming a lowest-level molding layer; forming a top RDL; and forming a top-level molding layer so as to fabricate a semiconductor package.

Abstract: An antibody or an antigen-binding portion thereof binding to CHI3L1 includes a heavy chain variable region and a light chain variable region. The antibody or the antigen-binding portion thereof targeting CHI3L1 not just inhibit activated AKT and ERK signals, cancer cells migration, tumor progression, tumor fibrosis, angiogenesis and cancer-induced muscle loss such as cachexia, but modulate TME toward an immunostimulatory phenotype.

Abstract: A method for forming a semiconductor device structure includes forming a plurality of fin structures from a substrate, each fin structure having first and second semiconductor layers alternatingly stacked, forming an isolation region around the fin structures, forming a first liner layer on exposed surfaces of the fin structures and the isolation region, forming a second liner layer on the first liner layer, selectively removing a portion of the second liner layer so that the second liner layer remains over sidewall of each fin structure, forming an insulating layer on the first and second liner layers, removing the second liner layer, forming a sacrificial gate structure over a portion of the fin structure and the insulating layer, removing a portion of the fin structure not covered by the sacrificial gate structure, forming a source/drain feature such that a gap is formed around and separate the source/drain feature from the insulating layer, and forming a sealing material on the source/drain feature and th

Abstract: Provided is a method for preparing a tissue section, including treating a tissue specimen with a clearing agent and at least one labeling agent to obtain a cleared and labeled tissue specimen; generating a three-dimensional (3D) image of the cleared and labeled tissue specimen; performing an image slicing procedure on the 3D image to generate a plurality of two-dimensional (2D) images; identifying a target 2D image among the plurality of 2D images to obtain a distance value of D1, which indicates the distance between the target 2D image and a predetermined surface of the 3D image; preparing a hardened tissue specimen from the cleared and labeled tissue specimen; and cutting the hardened tissue specimen near a predetermined site to obtain a tissue section, wherein the distance between the predetermined site and a surface of the hardened tissue specimen corresponding to the predetermined surface of the 3D image is D1.

Abstract: A method of fabricating a memory device includes forming a plurality of first nanostructures, a plurality of second nanostructures, a plurality of third nanostructures, and a plurality of fourth nanostructures; separating the plurality of first nanostructures and the plurality of second nanostructures with a dielectric fin structure; forming a first gate structure wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure; forming a second gate structure wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure; and forming a first interconnect structure coupled to one of the first gate structure or second gate structure. The dielectric structure also extends along the first lateral direction. The first and second gate structures extend along a second lateral direction perpendicular to the first lateral direction.

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side opposing the front side, a gate stack disposed on the front side of the substrate, a first source/drain feature and a second source/drain feature disposed in opposing sides of the gate stack, wherein each first source/drain feature and second source/drain feature comprises a first side and a second side, and the second side of the first source/drain feature and the back side of the substrate are at different elevations. The semiconductor device structure also includes a conductive feature in contact with the second side of the first source/drain feature, wherein a portion of the back side of the substrate is exposed to air.

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.

Abstract: Various embodiments include stacked transistors and methods of forming stacked transistors. In an embodiment, a device includes: a first nanostructure; a second nanostructure above the first nanostructure; a first gate structure extending along a top surface and a bottom surface of the first nanostructure; and a second gate structure extending along a top surface and a bottom surface of the second nanostructure. The first gate structure is disposed at a first side of the first nanostructure and a first side of the second nanostructure. The second gate structure is disposed at a second side of the first nanostructure and a second side of the second nanostructure. The second side of the first nanostructure is opposite the first side of the first nanostructure. The second side of the second nanostructure opposite the first side of the second nanostructure.

Abstract: A light-conversion material and a light-emitting device and a display device including the same are provided. The light-conversion material is represented by formula (I): MmDdAaCcEeGg:Rr (I). Wherein M is Ca, Sr, or Ba; D is Zn, Cd, or a combination thereof; A is B, Al, or Ga; C is Si; E is O, S, or Se; G is N, P, As, Sb, or Bi; and R is Eu, Sm, or Yb. The formula (I) is satisfied by 0.5?m?2; 1?d?4; 0?a?2; 0.1?c?3.5; 0.1?e?4; 0.5?g?5.5; and 0.1?r?1.

Abstract: A device includes a semiconductor substrate, a first transistor, a second transistor over the first transistor and a first isolation structure. The first transistor is on the semiconductor substrate. The first transistor comprises a first channel, a first source and a first drain. The first source and the first drain are on opposite sides of the first channel. The second transistor comprises a second channel, a second source and a second drain. The second source and the second drain are on opposite sides of the second channel. The first transistor is connected in series with the second transistor. The first isolation structure is vertically between the first drain and the second source.

Abstract: A structure for mounting a cooling fan easily and conveniently and in the correct orientation only includes a chassis and at least one fan module. The chassis has a block, a first nut, and a second nut. The fan module has at least one accessory. The block is mounted on the first nut or the second nut. When the block is fixed on the first nut, the fan module can only be placed and installed so as to blow air into the chassis, and when the block is fixed on the second nut, the fan module can only be installed so as to extract air out of the chassis, thereby ensuring the correct mode of operation. An electronic device and a server using the structure is also disclosed.

Abstract: A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.