Patents by Inventor Ching-Wen Hsiao

Ching-Wen Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978433
    Abstract: A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 10964610
    Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Publication number: 20210066226
    Abstract: Electrical devices, semiconductor packages and methods of forming the same are provided. One of the electrical devices includes a substrate, a conductive pad, a conductive pillar and a solder region. The substrate has a surface. The conductive pad is disposed on the surface of the substrate. The conductive pillar is disposed on and electrically connected to the conductive pad, wherein a top surface of the conductive pillar is inclined with respect to the surface of the substrate. The solder region is disposed on the top surface of the conductive pillar.
    Type: Application
    Filed: May 5, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Patent number: 10879228
    Abstract: A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution structure is lower than a topmost surface of the package substrate. A conductive connector electrically couples the redistribution structure to the package substrate. The conductive connector physically contacts a sidewall of the redistribution structure. A first integrated circuit die is bonded to the redistribution structure through first bonding structures and is bonded to the package substrate through second bonding structures. The first bonding structures and the second bonding structures have different sizes.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Publication number: 20200363773
    Abstract: The present disclosure provides a protection casing assembly for a wearable device. The protection casing assembly includes a main case and a frame. The main case has a first accommodation space and configured to allow a wearable device to be disposed detachably. When the wearable device is disposed in the first accommodation space, the wearable device and the main case define a second accommodation space adjacent to at a device surface of the wearable device. The frame is detachably disposed in the second accommodation space.
    Type: Application
    Filed: October 2, 2019
    Publication date: November 19, 2020
    Inventors: CHING-FU WANG, SHENG-CHE SU, PO-WEN HSIAO, CHIA-HO LIN
  • Publication number: 20200352045
    Abstract: The present disclosure provides a foldable apparatus for receiving a foldable device. The foldable apparatus includes a casing for receiving the foldable device. The casing includes a body and a bending zone. The body is for providing an accommodation to the foldable device. The bending zone is for folding the body from an unfolded position to a folded position. The bending zone includes a stress relaxation structure for retaining the body in the folded position and reversing the body to the unfolded position.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: CHING-FU WANG, SHENG-CHE SU, PO-WEN HSIAO, CHIA-HO LIN
  • Publication number: 20200328169
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 15, 2020
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Patent number: 10744207
    Abstract: The disclosure provides complexes comprising targeting units, methods for their production, and methods for their use. In some embodiments, complexes comprise therapeutic agents complexed with targeting units. In some embodiments, complexes comprise cells complexed with targeting units. In view of the foregoing, there is a need for improved modalities for targeting of therapeutics, in the area of immunotherapy and others. The present disclosure addresses these needs, and provides additional advantages as well.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: August 18, 2020
    Assignee: ACEPODIA, INC.
    Inventors: Amy A. Twite, Ching-Wen Hsiao, Sonny Hsiao, Cheng Liu, Hong Liu
  • Publication number: 20200251463
    Abstract: A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution structure is lower than a topmost surface of the package substrate. A conductive connector electrically couples the redistribution structure to the package substrate. The conductive connector physically contacts a sidewall of the redistribution structure. A first integrated circuit die is bonded to the redistribution structure through first bonding structures and is bonded to the package substrate through second bonding structures. The first bonding structures and the second bonding structures have different sizes.
    Type: Application
    Filed: April 20, 2020
    Publication date: August 6, 2020
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Publication number: 20200243410
    Abstract: Conductive structures and the redistribution circuit structures are disclosed. One of the conductive structures includes a first conductive layer and a second conductive layer. The first conductive layer is disposed in a lower portion of a dielectric layer, and the first conductive layer includes an upper surface with a protrusion at an edge. The second conductive layer is disposed in an upper portion of the dielectric layer and electrically connected to the first conductive layer. An upper surface of the second conductive layer is conformal with the upper surface of the first conductive layer.
    Type: Application
    Filed: April 20, 2020
    Publication date: July 30, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Patent number: 10700025
    Abstract: A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yen-Chang Hu, Ching-Wen Hsiao, Mirng-Ji Lii, Chung-Shi Liu, Chien Ling Hwang, Chih-Wei Lin, Chen-Shien Chen
  • Patent number: 10692789
    Abstract: A semiconductor package structure is provided. The structure includes a first semiconductor die having a first surface and a second surface opposite thereto. A first molding compound surrounds the first semiconductor die. A first redistribution layer (RDL) structure is disposed on the second surface of the first semiconductor die and laterally extends on the first molding compound. A second semiconductor die is disposed on the first RDL structure and has a first surface and a second surface opposite thereto. A second molding compound surrounds the second semiconductor die. A first protective layer covers a sidewall of the first RDL structure and a sidewall of the first molding compound.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: June 23, 2020
    Assignee: MediaTek Inc.
    Inventors: Nai-Wei Liu, Tzu-Hung Lin, I-Hsuan Peng, Ching-Wen Hsiao, Wei-Che Huang
  • Patent number: 10629509
    Abstract: Redistribution circuit structures and methods of forming the same are disclosed. One of the redistribution circuit structures includes a first conductive structure, a dielectric layer and a second conductive structure. The dielectric layer is disposed over and exposes a portion of the first conductive structure. The second conductive structure is disposed in the dielectric layer to electrically connect to the first conductive structure, and includes a first conductive layer and a second conductive layer disposed on and electrically connected to the first conductive layer. The first conductive layer includes a main portion and a conductive protrusion, the conductive protrusion is disposed on an entire edge of an upper surface of the main portion, and a top of the conductive protrusion is higher than the upper surface of the main portion.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Tu, Ching-Wen Hsiao, Sheng-Yu Wu, Ching-Hui Chen
  • Patent number: 10629580
    Abstract: A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution structure is lower than a topmost surface of the package substrate. A conductive connector electrically couples the redistribution structure to the package substrate. The conductive connector physically contacts a sidewall of the redistribution structure. A first integrated circuit die is bonded to the redistribution structure through first bonding structures and is bonded to the package substrate through second bonding structures. The first bonding structures and the second bonding structures have different sizes.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Publication number: 20200118978
    Abstract: A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen, Wei Sen Chang, Shou-Cheng Hu
  • Publication number: 20200105682
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Application
    Filed: February 1, 2019
    Publication date: April 2, 2020
    Inventors: Haochun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Publication number: 20200105728
    Abstract: A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen
  • Publication number: 20200091086
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu
  • Publication number: 20200083152
    Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Ching-Wen Hsiao, Ming-Da Cheng, Chih-Wei Lin, Chen-Shien Chen, Chih-Hua Chen, Chen-Cheng Kuo
  • Patent number: 10522473
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu