Patents by Inventor Ching-Wen Hsiao

Ching-Wen Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272664
    Abstract: A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiang-Jui Chu, Ching-Wen Hsiao, Hao-Chun Liu, Ming-Da Cheng, Young-Hwa Wu, Tao-Sheng Chang
  • Publication number: 20250080756
    Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, one or more model parameters of one or more cross-color models for the second-color block are determined. Then, cross-color predictors for the second-color block are determined, wherein one cross-color predictor value for the second-color block is generated for each second-color pixel of the second-color block by applying said one or more cross-color models to corresponding reconstructed or predicted first-color pixels. The input data associated with the second-color block is encoded using prediction data comprising the cross-color predictors for the second-color block at the encoder side, or the input data associated with the second-color block is decoded using the prediction data comprising the cross-color predictors for the second-color block at the decoder side.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 6, 2025
    Inventors: Man-Shu CHIANG, Olena CHUBACH, Yu-Ling HSIAO, Chia-Ming TSAI, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250063155
    Abstract: A method and apparatus for inter prediction in video coding system are disclosed. According to the method, input data associated with a current block comprising at least one colour block are received. A blending predictor is determined according to a weighted sum of at least two candidate predictions generated based on one or more first hypotheses of prediction, one or more second hypotheses of prediction, or both. The first hypotheses of prediction are generated based on one or more intra prediction modes comprising a DC mode, a planar mode or at least one angular modes. The second hypotheses of prediction are generated based on one or more cross-component modes and a collocated block of said at least one colour block. The input data associated with the colour block is encoded or decoded using the blending predictor.
    Type: Application
    Filed: December 20, 2022
    Publication date: February 20, 2025
    Inventors: Man-Shu CHIANG, Olena CHUBACH, Chia-Ming TSAI, Yu-Ling HSIAO, Chun-Chia CHEN, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250056008
    Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The system constructs two or more chroma prediction models based on luma and chroma samples neighboring the current block. The system applies the two or more chroma prediction models to incoming or reconstructed luma samples of the current block to produce two or more model predictions. The system computes predicted chroma samples by combining the two or more model predictions. The system uses the predicted chroma samples to reconstruct chroma samples of the current block or to encode the current block.
    Type: Application
    Filed: December 20, 2022
    Publication date: February 13, 2025
    Inventors: Yu-Ling HSIAO, Olena CHUBACH, Chun-Chia CHEN, Chia-Ming TSAI, Man-Shu CHIANG, Chih-Wei HSU, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250041340
    Abstract: The present invention provides a method of treating targeted abnormal cells that are resistant, refractory, insensitive, non-responsive, or inadequately responsive to an ingredient, as well as cytotoxic cells used therein, comprising administering an effective amount of the ingredient-complexed cytotoxic cells to a subject with the disease.
    Type: Application
    Filed: December 12, 2022
    Publication date: February 6, 2025
    Applicant: Acepodia Biotechnologies Ltd.
    Inventors: CHING-WEN HSIAO, ZIH-FEI CHENG, TAI-SHENG WU, YAN-LIANG LIN, HAO-KANG LI, SAI-WEN TANG, HSIU-PING YANG, SHIH-CHIA HSIAO
  • Publication number: 20250039356
    Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coding system derives multiple prediction linear models based on luma and chroma samples neighboring the current block. The video coding system constructs a composite linear model based on the multiple prediction linear models. The video coding system applies the composite linear model to incoming or reconstructed luma samples of the current block to generate a chroma predictor of the current block. The video coding system uses the chroma predictor to reconstruct chroma samples of the current block or to encode the current block.
    Type: Application
    Filed: December 29, 2022
    Publication date: January 30, 2025
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Yu-Ling HSIAO, Man-Shu CHIANG, Chih-Wei HSU, Olena CHUBACH, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250024072
    Abstract: A method and apparatus for video coding system that uses intra prediction based on cross-colour linear model are disclosed. According to the method, model parameters for a first-colour predictor model are determined and the first-colour predictor model provides a predicted first-colour pixel value according to a combination of at least two corresponding reconstructed second-colour pixel values. According to another method, the first-colour predictor model provides a predicted first-colour pixel value based on a second degree model or higher of one or more corresponding reconstructed second-colour pixel values. First-colour predictors for the current first-colour block are determined according to the first-colour prediction model. The input data are then encoded at the encoder side or decoded at the decoder side using the first-colour predictors.
    Type: Application
    Filed: October 26, 2022
    Publication date: January 16, 2025
    Inventors: Olena CHUBACH, Ching-Yeh CHEN, Tzu-Der CHUANG, Chun-Chia CHEN, Man-Shu CHIANG, Chia-Ming TSAI, Yu-Ling HSIAO, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20240379428
    Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Hao Chun Liu, Po-Hao Tsai, Chih-Hsien Lin, Ching-Wen Hsiao
  • Publication number: 20240379589
    Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Inventors: Wei-Han CHIANG, Chun-Hung CHEN, Ching-Ho CHENG, Ching-Wen Hsiao, Hong-Seng SHUE, Ming-Da CHENG, Wei Sen CHANG
  • Publication number: 20240381570
    Abstract: An immersion cooling system includes a cooling tank, a busbar and two busbar protection modules. The busbar is disposed in the cooling tank. The two busbar protection modules are disposed at opposite sides of the busbar. Each of the two busbar protection modules includes a base, a driving member and a cover. The driving member is pivotally connected to the base. The cover is pivotally connected to the driving member. Two covers of the two busbar protection modules extend toward each other to cover the busbar. When two driving members of the two busbar protection modules are pushed, the two driving members rotate to drive the two covers to move away from each other, such that the busbar is exposed between the two covers.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 14, 2024
    Applicant: Wiwynn Corporation
    Inventors: Ching-Wen Hsiao, Yun-Ya Chiu, Hsien-Chieh Hsieh
  • Publication number: 20240363569
    Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 31, 2024
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ching-Wen Hsiao, Hong-Seng Shue, Ming-Da Cheng
  • Publication number: 20240347578
    Abstract: A manufacturing method of a semiconductor device includes: forming a first dielectric layer on inductor traces, openings of the first dielectric layer exposing the inductor traces; disposing a buffer material on the first dielectric layer and the inductor traces in the openings; sequentially disposing an etch stop material and a ferromagnetic material on the buffer material; removing the ferromagnetic material from over the openings to form a core material layer covering a first area; removing the etch stop and buffer materials from the openings to form an etch stop layer and a buffer layer, where the etch stop and buffer layers cover a second area, the first area is smaller than and within the second area; forming a second dielectric layer on the first dielectric layer to embed the buffer, etch stop, and core material layers; and forming inductor vias extending through the first and second dielectric layers.
    Type: Application
    Filed: June 24, 2024
    Publication date: October 17, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsien Kuo, Hon-Lin Huang, Han-Yi Lu, Ching-Wen Hsiao, Alexander Kalnitsky
  • Patent number: 12114450
    Abstract: An electronic device includes a base, a multi-stage sensor, a top cover, and a side cover. The multi-stage sensor is configured to sense a sensed area. The top cover includes a top-sensed element, and the top cover is detachably connected to a top side of the base, so that the top-sensed element can be selectively in or not in the sensed area. The side cover includes a side-sensed element, and the side cover is detachably adjacent to a front side of the base, so that the side-sensed element can be selectively in or not in the sensed area. In response to that only the top-sensed element is in the sensed area, the multi-stage sensor outputs a first signal. In response to that neither the top-sensed element nor the side-sensed element is in the sensed area, the multi-stage sensor outputs a second signal.
    Type: Grant
    Filed: November 2, 2022
    Date of Patent: October 8, 2024
    Assignee: WIWYNN CORPORATION
    Inventors: Ching-Wen Hsiao, Chia-Hung Yen
  • Publication number: 20240332220
    Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.
    Type: Application
    Filed: June 13, 2024
    Publication date: October 3, 2024
    Inventors: Hong-Seng Shue, Yao-Chun Chuang, Yu-Tse Su, Chen-Shien Chen, Ching-Wen Hsiao, Ming-Da Cheng
  • Publication number: 20240266304
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 8, 2024
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 12057423
    Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: August 6, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ching-Wen Hsiao, Hong-Seng Shue, Ming-Da Cheng
  • Patent number: 12057468
    Abstract: An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsien Kuo, Hon-Lin Huang, Han-Yi Lu, Ching-Wen Hsiao, Alexander Kalnitsky
  • Patent number: 12051622
    Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Hao Chun Liu, Po-Hao Tsai, Chih-Hsien Lin, Ching-Wen Hsiao
  • Patent number: 12040289
    Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Seng Shue, Ming-Da Cheng, Ching-Wen Hsiao, Yao-Chun Chuang, Yu-Tse Su, Chen-Shien Chen
  • Publication number: 20240197872
    Abstract: Provided herein are novel compositions enriched in gdT cells with high therapeutic potential. Methods to produce such compositions and methods of uses thereof in adoptive immunotherapies are also provided.
    Type: Application
    Filed: April 14, 2022
    Publication date: June 20, 2024
    Applicant: Acepodia Biotechnologies Ltd.
    Inventors: CHING-WEN HSIAO, ZIH-FEI CHENG, TAI-SHENG WU, HAO-KANG LI, HSIU-PING YANG, CHIA-YUN LEE, SAI-WEN TANG, YI-HUNG OU, YAN-LIANG LIN, SHIH-CHIA HSIAO