Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, package-side bump structures located on a first side of the interconnect-level dielectric material layers, at least one dielectric capping layer located on a second side of the interconnect-level dielectric material layers, a bonding-level dielectric layer located on the at least one dielectric capping layer, metallic pad structures including pad via portions embedded in the at least one dielectric capping layer and pad plate portions embedded in the bonding-level dielectric layer, and an edge seal ring structure vertically extending from a first horizontal plane including bonding surfaces of the package-side bump structures to a second horizontal plane including distal planar surfaces of the metallic pad structures.

Abstract: An integrated circuit has corner regions and non-corner regions between the corner regions and includes a semiconductor substrate, conductive pads, passivation layer, post-passivation layer, first conductive posts, and second conductive posts. The conductive pads are disposed over the semiconductor substrate. The passivation layer and the post-passivation layer are sequentially disposed over the conductive pads. The first conductive posts and the second conductive posts are disposed on the post-passivation layer and are electrically connected to the conductive pads. The first conductive posts are disposed in the corner regions and the second conductive posts are disposed in the non-corner regions. Each of the first conductive posts has a body portion and a protruding portion connected to the body portion. A central axis of the body portion of the first conductive post has an offset from a central axis of the protruding portion of the first conductive post.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The conductive pillar is formed in one piece, the conductive pillar has a lower surface and a bottom protruding portion protruding from the lower surface, the bottom protruding portion passes through the insulating layer over the first conductive line, the bottom protruding portion is in direct contact with the first conductive line, and a first linewidth of a first portion of the first conductive line under the conductive pillar is less than a width of the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: The present invention provides a human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line. These human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line does not include synthetic, genetically modified or purposely deliberately delivered polynucleotide encoding the CD16 receptor and are non-tumorigenic cell lines. Therefore, this human CD16+ natural killer cell line and a CAR-expressing human CD16+ natural killer cell line might provide considerable long-term safety for disease treatment.

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

Abstract: A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Abstract: A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Abstract: A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

Abstract: Electrical devices, semiconductor packages and methods of forming the same are provided. One of the electrical devices includes a substrate, a conductive pad, a conductive pillar and a solder region. The substrate has a surface. The conductive pad is disposed on the surface of the substrate. The conductive pillar is disposed on and electrically connected to the conductive pad, wherein a top surface of the conductive pillar is inclined with respect to the surface of the substrate. The solder region is disposed on the top surface of the conductive pillar.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.

Abstract: An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Abstract: An organic interposer includes interconnect-level dielectric material layers embedding redistribution interconnect structures, at least one dielectric capping layer overlying a topmost interconnect-level dielectric material layer, a bonding-level dielectric layer overlying the at least one dielectric capping layer, and a dual-layer inductor structure, which may include a lower conductive coil embedded within the topmost interconnect-level dielectric material layer, a conductive via structure vertically extending through the at least one dielectric capping layer, and an upper conductive coil embedded within the bonding-level dielectric layer and comprising copper.