Patents by Inventor Ching-Wen Hsiao

Ching-Wen Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110227216
    Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer.
    Type: Application
    Filed: March 16, 2010
    Publication date: September 22, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hung Tseng, Chen-Shien Chen, Chen-Cheng Kuo, Chih-Hua Chen, Ching-Wen Hsiao
  • Publication number: 20110193227
    Abstract: Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %.
    Type: Application
    Filed: March 22, 2010
    Publication date: August 11, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Ching-Wen Hsiao, Chen-Cheng Kuo, Chen-Shien Chen
  • Publication number: 20110193220
    Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 11, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Ching-Wen Hsiao
  • Publication number: 20110186986
    Abstract: A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 4, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chen-Cheng Kuo, Ching-Wen Hsiao, Chen-Shien Chen
  • Publication number: 20110101526
    Abstract: An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.
    Type: Application
    Filed: November 16, 2009
    Publication date: May 5, 2011
    Inventors: Ching-Wen Hsiao, Jiun Yi Wu, Ru-Ying Huang, Chen-Shien Chen
  • Publication number: 20110101519
    Abstract: An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a copper bump at a main surface of the first work piece and having a first dimension; and a nickel-containing barrier layer over and adjoining the copper bump. The second work piece is bonded to the first work piece and includes a bond pad at a main surface of the second work piece; and a solder mask at the main surface of the second work piece and having a solder resist opening with a second dimension exposing a portion of the bond pad. A ratio of the first dimension to the second dimension is greater than about 1. Further, a solder region electrically connects the copper bump to the bond pad, with a vertical distance between the bond pad and the copper bump being greater than about 30 ?m.
    Type: Application
    Filed: July 23, 2010
    Publication date: May 5, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Yao-Chun Chuang, Chen-Shien Chen, Chen-Cheng Kuo, Ru-Ying Huang
  • Patent number: 7929564
    Abstract: An apparatus and a method for loading a predetermined number of bits into a plurality of sub-channels are provided. The apparatus comprises a sort module, a calculation module, and a decision module. The sort module is configured to sort the sub-channels into a plurality of sorted sub-channels according to the quality value of each of the sub-channels. The calculation module is configured to calculate the difference value for each of the sorted sub-channels, except for the first sorted sub-channel, according to the corresponding quality value. The decision module is configured to decide a number of bits for each of the sorted sub-channels according to the difference values, wherein a summation of the numbers is equal to the predetermined number. The apparatus and the method are able to load bits efficiently according to the difference values.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: April 19, 2011
    Assignee: Mediatek Inc.
    Inventors: Ta-Sung Lee, Ching-Wen Hsiao
  • Publication number: 20110068465
    Abstract: A flip-chip packaging assembly and integrated circuit device are disclosed. An exemplary flip-chip packaging assembly includes a first substrate; a second substrate; and joint structures disposed between the first substrate and the second substrate. Each joint structure comprises an interconnect post between the first substrate and the second substrate and a joint solder between the interconnect post and the second substrate, wherein the interconnect post exhibits a width and a first height. A pitch defines a distance between each joint structure. The first height is less than half the pitch.
    Type: Application
    Filed: November 23, 2009
    Publication date: March 24, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Wei Shen, Chen-Shien Chen, Chen-Cheng Kuo, Chih-Hua Chen, Ching-Wen Hsiao
  • Publication number: 20110049706
    Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.
    Type: Application
    Filed: July 7, 2010
    Publication date: March 3, 2011
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
  • Patent number: 7888236
    Abstract: A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas.
    Type: Grant
    Filed: May 14, 2007
    Date of Patent: February 15, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Ping Pu, Bai-Yao Lou, Dean Wang, Ching-Wen Hsiao, Kai-Ming Ching, Chen-Cheng Kuo, Wen-Chih Chiou, Ding-Chung Lu, Shang-Yun Hou
  • Publication number: 20100330788
    Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 30, 2010
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua YU, Kuo-Ching HSU, Chen-Shien CHEN, Ching-Wen HSIAO
  • Publication number: 20100330798
    Abstract: An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×108 Ohm-cm.
    Type: Application
    Filed: March 31, 2010
    Publication date: December 30, 2010
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hon-Lin Huang, Ching-Wen Hsiao, Kuo-Ching Hsu, Chen-Shien Chen
  • Patent number: 7838333
    Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: November 23, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin
  • Publication number: 20100117201
    Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.
    Type: Application
    Filed: November 11, 2009
    Publication date: May 13, 2010
    Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming-Hong Tseng, Chen-Shien Chen
  • Publication number: 20100112757
    Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 6, 2010
    Applicant: Industrial Technology Research Institute
    Inventors: Shou-Lung CHEN, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin
  • Publication number: 20100102453
    Abstract: A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.
    Type: Application
    Filed: October 28, 2008
    Publication date: April 29, 2010
    Inventors: Ming-Hong Tseng, Kai-Ming Ching, Chen-Shien Chen, Ching-Wen Hsiao, Hon-Lin Huang, Tsung-Ding Wang
  • Patent number: 7632707
    Abstract: The present invention discloses an electronic device package and a method of the package. In particular, an electronic device package and a method of the package suitable for a bumpless electronic device package with enhanced electrical performance and heat-dissipation efficiency are disclosed. The method comprises: providing a substrate having a plurality of vias and a plurality of electronic devices; forming a gluing layer on a surface of the substrate and fixing the electronic devices on the gluing layer, wherein the electronic devices have I/O units aligned with the vias respectively; forming a plurality of fixing layers in the gaps between the electronic devices; trenching a plurality of openings aligned with the vias respectively in the fixing layer; forming a plurality of metallic conductive units in the vias, the openings and part of the surface of the substrate; and forming a passivation layer over the other surface of the substrate.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: December 15, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Shou-Lung Chen, Ching-Wen Hsiao, Yu-Hua Chen, Jeng-Dar Ko, Jyh-Rong Lin
  • Publication number: 20090232156
    Abstract: An apparatus and a method for loading a predetermined number of bits into a plurality of sub-channels are provided. The apparatus comprises a sort module, a calculation module, and a decision module. The sort module is configured to sort the sub-channels into a plurality of sorted sub-channels according to the quality value of each of the sub-channels. The calculation module is configured to calculate the difference value for each of the sorted sub-channels, except for the first sorted sub-channels, according to the corresponding quality value. The decision module is configured to decide a number of bits for each of the sorted sub-channels according to the difference values, wherein a summation of the numbers is equal to the predetermined number. The apparatus and the method are able to load bits efficiently according to the difference values.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 17, 2009
    Applicant: MEDIATEK INC.
    Inventors: Ta-Sung Lee, Ching-Wen Hsiao
  • Patent number: 7572676
    Abstract: This invention relates to a packaging structure and method of an image sensor module. The method comprises: providing a transparent substrate having a first patterned conductive layer; carrying an image sensor integrated circuit chip having a photosensitive active area and at least one passive chip on the transparent substrate, wherein the photosensitive active area faces the transparent substrate; forming an insulating build-up film over the transparent substrate; and forming a plurality of conductive vias in the insulating build-up film wherein the ends of the conductive vias are connected with the passive chip or the first patterned conductive layer of the transparent substrate while the other ends of the conductive vias are exposed on the surface of the insulating build-up film. The packaging method is capable of down-sizing the construction of the image sensor module and simplifying the processing steps.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: August 11, 2009
    Assignee: Industrial Technology Research Institute
    Inventors: Fang-Jun Leu, Shou-Lung Chen, Ching-Wen Hsiao, Shan-Pu Yu, Jyh-Rong Lin, I-Hsuan Peng, Jian-Shu Wu, Hui-Mei Wu, Chien-Wei Chieh
  • Patent number: 7554639
    Abstract: A method to control the pretilt angle of a liquid crystal device is disclosed. The claimed invention provides two substrates and at least one vertical alignment layers, which are fabricated on one side of each substrate and are opposite to each other. Moreover, a liquid crystal layer is sandwiched between the alignment layers, and the preferred embodiment of the liquid crystal device has an Optically Compensated Birefrigence (OCB) configuration. More particularly, before the process of alignment for the liquid crystal device is performed, a pretilt angle disclosed in the present invention is adjusted since at least one vertical alignment layer is treated with a particle beam generated by plasma or ions. The pretilt angle can range between 5 and 85 degrees.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: June 30, 2009
    Assignees: Taiwan TFT LCD Association, Chunghwa Picture Tubes, Ltd., Au Optronics Corp., Quanta Display Inc., Hannstar Display Corp., Chi Mei Optoelectronics Corp., Industrial Technology Research Institute, Toppoly Optoelectronics Corp.
    Inventors: Ching-Wen Hsiao, Bang-Hao Wu, Hsin-Chun Chiang, Yu-Ming Chen