Patents by Inventor Ching Wu

Ching Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154883
    Abstract: Various embodiments herein provide techniques related to sixth generation (6G) system architecture and functions. For example, embodiments may relate to one or more of: Design principle and system architecture; Orchestration frontend service; Dynamic device-network computing scaling; RDMA over radio; Cloud workload offloading to network; Computing-embedded air interface; Service chain aware transport; and/or Enabling Al capabilities. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 11, 2022
    Publication date: May 9, 2024
    Inventors: Qian Li, Zongrui Ding, Geng Wu, Sangeetha L. Bangolae, Sudeep Palat, Alexandre Saso Stojanovski, Thomas Luetzenkirchen, Ching-Yu Liao, Abhijeet Kolekar
  • Publication number: 20240151746
    Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system uses a cooling fluid supply module for the cooling of the pogo pin, and the cooling fluid may be either a coolant or a cooling gas. When an electronic device is accommodated in the chip socket, the cooling fluid supply module supplies a cooling fluid into the chip socket through the cooling fluid supply channel and the inlet, and the cooling fluid passes through the pogo pins and then flows into the cooling fluid discharge channel through the outlet. In the present invention, the cooling fluid is mainly used to cool not only the pogo pins in the chip socket but also the bottom surface of the electronic device and the solder ball contacts on the bottom surface.
    Type: Application
    Filed: April 27, 2023
    Publication date: May 9, 2024
    Inventors: I-Shih TSENG, I-Ching TSAI, Xin-Yi WU, Chin-Yi OUYANG
  • Patent number: 11978740
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Harry-Hak-Lay Chuang, Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien Hung Liu, Tsung-Hao Yeh, Hsien Jung Chen
  • Publication number: 20240142492
    Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: I-Shih TSENG, Xin-Yi WU, I-Ching TSAI, Chin-Yi OUYANG
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240146287
    Abstract: A frequency mixing circuit includes: a first transistor and a second transistor. The first transistor has a control terminal, a first terminal and a second terminal. The control terminal of the first transistor is configured to receive an oscillation signal, the first terminal of the first transistor is configured to output a mixed signal, and the second terminal of the first transistor is configured to receive a source signal. The second transistor has a control terminal, a first terminal and a second terminal. The control terminal of the second transistor is coupled to the second terminal of the first transistor, the first terminal of the second transistor is coupled to the first terminal of the first transistor, and the second terminal of the second transistor is coupled to the control terminal of the first transistor.
    Type: Application
    Filed: September 6, 2023
    Publication date: May 2, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Yi-Ching Wu, Chia-Jun Chang
  • Publication number: 20240139142
    Abstract: Provided is a method for preventing or treating a liver disease, including administering a therapeutically effective amount of pharmaceutical composition to a subject in need, and the pharmaceutical composition includes the isothiocyanate structural modified compound and a pharmaceutically acceptable carrier thereof.
    Type: Application
    Filed: September 14, 2023
    Publication date: May 2, 2024
    Applicants: TAIPEI VETERANS GENERAL HOSPITAL, NATIONAL YANG MING CHIAO TUNG UNIVERSITY, PHARMAESSENTIA CORPORATION
    Inventors: Jaw-Ching WU, Yung-Sheng CHANG, Kuo-Hsi KAO, Chan-Kou HWANG, Ko-Chung LIN
  • Publication number: 20240136346
    Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.
    Type: Application
    Filed: April 17, 2023
    Publication date: April 25, 2024
    Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
  • Publication number: 20240136293
    Abstract: Provided are a package structure having a joint structure and a method of forming the same. The package structure includes: a first under bump metallurgy (UBM) structure disposed on a first dielectric layer, wherein the first UBM structure at least comprises: a barrier layer embedded in the first dielectric layer; and an upper metal layer disposed over the barrier layer, wherein a sidewall of the barrier layer is laterally offset outward from a sidewall of the upper metal layer, and a portion of a top surface of the barrier layer is exposed by the first dielectric layer; and a solder layer disposed on the first UBM structure and contacting the upper metal layer.
    Type: Application
    Filed: January 31, 2023
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Wen-Chih Chiou, Ying-Ching Shih
  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20240126327
    Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
  • Publication number: 20240128211
    Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 18, 2024
    Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
  • Patent number: 11961732
    Abstract: A method includes depositing a first work-function layer and a second work-function layer in a first device region and a second device region, respectively, and depositing a first fluorine-blocking layer and a second fluorine-blocking layer in the first device region and the second device region, respectively. The first fluorine-blocking layer is over the first work-function layer, and the second fluorine-blocking layer is over the second work-function layer. The method further includes removing the second fluorine-blocking layer, and forming a first metal-filling layer over the first fluorine-blocking layer, and a second metal-filling layer over the second work-function layer.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ching Lee, Chung-Chiang Wu, Shih-Hang Chiu, Hsuan-Yu Tung, Da-Yuan Lee
  • Publication number: 20240117172
    Abstract: A composition and a manufacturing method of a highly flame-retardant and low-smoke injection-molded polyvinyl chloride pipe are provided. The composition includes a polyvinyl chloride resin material, a chlorinated polyvinyl chloride resin material, a flame retardant additive and a carbon forming additive. A first number-average degree of polymerization (DPn) of the polyvinyl chloride resin material is between 600 and 1,000. A second number-average degree of polymerization of the chlorinated polyvinyl chloride resin material is between 600 and 800. A difference between the first number-average degree of polymerization and the second number-average degree of polymerization is within 400. The flame retardant additive is a phosphorus-containing flame retardant modified by a modifier. A total added amount of the flame retardant additive and the carbon forming additive in the composition is not greater than 3 PHR.
    Type: Application
    Filed: November 29, 2022
    Publication date: April 11, 2024
    Inventors: TE-CHAO LIAO, HAN-CHING HSU, CHUN-LAI CHEN, WEN-YI WU
  • Publication number: 20240117342
    Abstract: An construction method of an embryonic chromosome signal library is provided. The construction method comprises obtaining an embryo and performing whole-genome amplification and next-generation sequencing to obtain a first chromosome signal; mapping the first chromosome signal to a chromosome reference signal to obtain a second chromosome signal; dividing the second chromosome signal within a predetermined interval range to obtain a third chromosome signal; and performing a regression correction on the sequencing read count (RC) of the third chromosome signal to obtain an embryonic chromosome signal library. Furthermore, a detection method and system of embryonic chromosomes are also provided. Thereby, the information comparison of the embryo chromosome signal library is used to determine whether the pre-implantation embryo is abnormal or not to achieve pre-implantation chromosome screening of pre-implantation embryos.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 11, 2024
    Inventors: LI-JEN SU, SHAO-PING WENG, YU-YU YEN, LI-CHING WU, HUI-YIN CHIU, JUI-HUNG KAO
  • Publication number: 20240117174
    Abstract: A PVC resin composition and a method for manufacturing a pipe having high heat resistance and transparency are provided. The PVC resin composition includes 100 phr of a PVC resin, 0.5 phr to 5 phr of a modifier, and 1 phr to 10 phr of a heat resistance improving agent. A degree of polymerization of the PVC resin is from 800 to 1,350. The modifier is a polymer containing a first monomer and a second monomer. The first monomer is ethylene or a derivative of the ethylene, and the second monomer is a polyester.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 11, 2024
    Inventors: TE-CHAO LIAO, HAN-CHING HSU, CHUN-LAI CHEN, WEN-YI WU
  • Publication number: 20240117176
    Abstract: A chlorinated polyvinyl chloride resin composition, an extruded sheet and a method for manufacturing the same are provided. The chlorinated polyvinyl chloride resin composition includes a chlorinated polyvinyl chloride resin and a plasticizing processing aid. The chlorinated polyvinyl chloride resin has an amount of 80 parts by weight to 120 parts by weight, a degree of polymerization of from 500 to 1,100, and a chlorine content of from 60% to 75%. The plasticizing processing aid includes a vinyl chloride graft copolymer and an acrylic compound. A grafted functional group of the vinyl chloride graft copolymer is at least one of polyol ester and ethylene vinyl acetate.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 11, 2024
    Inventors: TE-CHAO LIAO, HAN-CHING HSU, CHUN-LAI CHEN, WEN-YI WU
  • Publication number: 20240117173
    Abstract: A composition and a manufacturing method of a highly flame-retardant and low-smoke extruded polyvinyl chloride pipe are provided. The composition includes a polyvinyl chloride resin material, a flame retardant additive and a carbon forming additive. The polyvinyl chloride resin material is in an amount between 10 PHR (parts per hundred resin) and 90 PHR. The flame retardant additive is in an amount between 0.5 PHR and 2.0 PHR, and is a phosphorus-containing flame retardant modified by a modifier. The carbon forming additive is in an amount between 0.2 PHR and 1.0 PHR. The carbon forming additive is at least one material selected from a group consisting of zinc chloride, zinc stearate, calcium stearate, zinc hydroxystannate, anhydrous zinc stannate, zinc phosphate and zirconium phosphate. A total added amount of the flame retardant additive and the carbon forming additive in the composition is not greater than 3 PHR.
    Type: Application
    Filed: November 29, 2022
    Publication date: April 11, 2024
    Inventors: TE-CHAO LIAO, HAN-CHING HSU, CHUN-LAI CHEN, WEN-YI WU
  • Patent number: 11955721
    Abstract: An antenna apparatus, a communication apparatus, and a steering adjustment method thereof are provided. The antenna apparatus includes an antenna structure. The antenna structure includes an antenna unit. The antenna unit includes i feeding ports, where i is a positive integer larger than 2. A vector of each of the feeding ports is controlled independently. In the steering adjustment method, a designated direction is determined, where the designated direction corresponds to beam directionality of the antenna structure. In addition, the vectors of the feeding ports of the antenna unit are configured according to the designated direction. Accordingly, the antenna size can be reduced, and beam steering in multiple directions would be achieved.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 9, 2024
    Assignee: Gemtek Technology Co., Ltd.
    Inventors: Chung-Kai Yang, Sin-Liang Chen, Hsu-Sheng Wu, Hsiao-Ching Chien
  • Patent number: 11955459
    Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih