Patents by Inventor Ching-Yi Chen
Ching-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973958Abstract: Methods and apparatus of video coding using sub-block based affine mode are disclosed. According to this method, control-point motion vectors (MVs) associated with the affine mode are determined for a block. A sub-block MV is derived for a target sub-block of the block from the control-point MVs for the block. A prediction offset is determined for a target pixel of the target sub-block using information comprising a pixel MV offset from the sub-block MV for the target pixel according to Prediction Refinement with Optical Flow (PROF). The target pixel of the target sub-block is encoded or decoded using a modified predictor. The modified prediction is generated by clipping the prediction offset to a target range and combining the clipped prediction offset with an original predictor.Type: GrantFiled: September 22, 2020Date of Patent: April 30, 2024Assignee: HFI INNOVATION INC.Inventors: Tzu-Der Chuang, Ching-Yeh Chen, Zhi-Yi Lin
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Publication number: 20240136227Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Patent number: 11967591Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.Type: GrantFiled: August 6, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Jyh Chwen Frank Lee
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Patent number: 11949852Abstract: A method and apparatus of video coding, where according to one method, input data related to a current block in a current picture are received at a video encoder side or compressed data comprising the current block are received at a video decoder side. A first syntax at a high level in a video bitstream regarding residual coding type is signaled at the encoder side or parsed at the decoder side. A target coding mode is determined for the current block based on information comprising a value of the first syntax. The current block is encoded at the encoder side or decoded at the decoder side according to the target coding mode. The high level may correspond to a slice header or a picture header.Type: GrantFiled: September 16, 2020Date of Patent: April 2, 2024Assignee: HFI INNOVATION INC.Inventors: Zhi-Yi Lin, Tzu-Der Chuang, Ching-Yeh Chen
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Patent number: 11930174Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.Type: GrantFiled: December 30, 2019Date of Patent: March 12, 2024Assignee: HFI INNOVATION INC.Inventors: Chia-Ming Tsai, Tzu-Der Chuang, Chih-Wei Hsu, Ching-Yeh Chen, Zhi-Yi Lin
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Publication number: 20240072017Abstract: A pixel unit includes a red LED chip, a green LED chip, and a blue LED chip. Each of these chips has an optical density concentration zone and a reference line passing through the geometric center of the top-view shape of the chip. The optical density concentration zone of each of these chips is deviated to one side of the respective reference line of the chip. The reference lines of the chips are parallel to each other. The optical density concentration zones of the chips are all deviated to the same side of the respective reference line.Type: ApplicationFiled: August 16, 2023Publication date: February 29, 2024Inventors: Ching-Yi CHEN, Wei-An CHEN
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Patent number: 11916022Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.Type: GrantFiled: June 7, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yeong-Jyh Lin, Ching I Li, De-Yang Chiou, Sz-Fan Chen, Han-Jui Hu, Ching-Hung Wang, Ru-Liang Lee, Chung-Yi Yu
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Patent number: 11901229Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.Type: GrantFiled: May 23, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Publication number: 20230395426Abstract: Provided is a conductive structure and a method for forming such a structure. The method includes forming a treatable layer by depositing a layer comprising a metal over a structure; performing a directional treatment process on a targeted portion of the treatable layer to convert the targeted portion to a material different from a non-targeted portion of the treatable layer, wherein the directional treatment process is selected from the group consisting of nitridation, oxidation, chlorination, carbonization; and selectively removing the non-targeted portion from the structure, wherein the targeted portion remains over the structure.Type: ApplicationFiled: June 1, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsiang Chao, Shu-Lan Chang, Ching-Yi Chen, Shih-Wei Yeh, Pei Shan Chang, Ya-Yi Cheng, Yu-Chen Ko, Yu-Shiuan Wang, Chun-Hsien Huang, Hung-Chang Hsu, Chih-Wei Chang, Ming-Hsing Tsai, Wei-Jung Lin
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Patent number: 11792900Abstract: A dimmer circuit includes a light emitting module, a first current source, a digital-to-analog converter, a switch, a second current source and a pulse width modulation generator. The light emitting module is for emitting light according to a driving current. The first current source includes a first terminal coupled to a second terminal of the light emitting module. The digital-to-analog converter is for generating a DC voltage according to a DC dimming code signal to control the first current source. The switch includes a first terminal coupled to a second terminal of the light emitting module. The second current source includes a first terminal coupled to a second terminal of the switch. The PWM generator is for generating a PWM voltage according to the PWM dimming code signal to control the second current source.Type: GrantFiled: October 25, 2022Date of Patent: October 17, 2023Assignee: RICHTEK TECHNOLOGY CORP.Inventors: Ching-Yi Chen, Hsing-Shen Huang
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Publication number: 20230260836Abstract: A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.Type: ApplicationFiled: May 13, 2022Publication date: August 17, 2023Inventors: Pei Shan Chang, Yi-Hsiang Chao, Chun-Hsien Huang, Peng-Hao Hsu, Kevin Lee, Shu-Lan Chang, Ya-Yi Cheng, Ching-Yi Chen, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20230187201Abstract: A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.Type: ApplicationFiled: February 2, 2023Publication date: June 15, 2023Inventors: Ching-Yi Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Publication number: 20230141723Abstract: A dimmer circuit includes a light emitting module, a first current source, a digital-to-analog converter, a switch, a second current source and a pulse width modulation generator. The light emitting module is for emitting light according to a driving current. The first current source includes a first terminal coupled to a second terminal of the light emitting module. The digital-to-analog converter is for generating a DC voltage according to a DC dimming code signal to control the first current source. The switch includes a first terminal coupled to a second terminal of the light emitting module. The second current source includes a first terminal coupled to a second terminal of the switch. The PWM generator is for generating a PWM voltage according to the PWM dimming code signal to control the second current source.Type: ApplicationFiled: October 25, 2022Publication date: May 11, 2023Applicant: RICHTEK TECHNOLOGY CORP.Inventors: Ching-Yi Chen, Hsing-Shen Huang
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Patent number: 11594410Abstract: A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.Type: GrantFiled: August 24, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Yi Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Publication number: 20220277997Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.Type: ApplicationFiled: May 23, 2022Publication date: September 1, 2022Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Patent number: 11342225Abstract: A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.Type: GrantFiled: July 31, 2019Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yi Chen, Sheng-Hsuan Lin, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Publication number: 20220110445Abstract: A storage rack contains: a rectangular platform, two support feet, a rectangular plane, two long fringes, two short fringes, four circular orifices, four oval orifices, and two grips which. The two support feet are connected on the rectangular platform, and a respective support foot has a first inward bending portion and a second inward bending portion which are formed on two free ends of two tops of the respective support foot. Each of the first inward bending portion and the second inward bending portion has an arcuate face and an insertion, the arcuate face corresponds to a respective oval orifice of a respective long fringe of the rectangular platform, and the insertion corresponds to a respective circular orifice of the respective long fringe of the rectangular platform, such that the insertion is rotatably accommodated into the respective circular orifice to expand or retract the respective support foot freely.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Inventor: Ching-Yi CHEN
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Patent number: 11278115Abstract: A storage rack contains: a rectangular platform, two support feet, a rectangular plane, two long fringes, two short fringes, four circular orifices, four oval orifices, and two grips which. The two support feet are connected on the rectangular platform, and a respective support foot has a first inward bending portion and a second inward bending portion which are formed on two free ends of two tops of the respective support foot. Each of the first inward bending portion and the second inward bending portion has an arcuate face and an insertion, the arcuate face corresponds to a respective oval orifice of a respective long fringe of the rectangular platform, and the insertion corresponds to a respective circular orifice of the respective long fringe of the rectangular platform, such that the insertion is rotatably accommodated into the respective circular orifice to expand or retract the respective support foot freely.Type: GrantFiled: October 8, 2020Date of Patent: March 22, 2022Inventor: Ching-Yi Chen
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Patent number: D1012943Type: GrantFiled: April 6, 2021Date of Patent: January 30, 2024Assignee: Acer Medical Inc.Inventor: Ching-Yi Chen
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Patent number: D1024126Type: GrantFiled: January 2, 2023Date of Patent: April 23, 2024Assignee: Acer Medical Inc.Inventor: Ching-Yi Chen