Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: A method and apparatus of video coding, where according to one method, input data related to a current block in a current picture are received at a video encoder side or compressed data comprising the current block are received at a video decoder side. A first syntax at a high level in a video bitstream regarding residual coding type is signaled at the encoder side or parsed at the decoder side. A target coding mode is determined for the current block based on information comprising a value of the first syntax. The current block is encoded at the encoder side or decoded at the decoder side according to the target coding mode. The high level may correspond to a slice header or a picture header.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A method and apparatus for block partition are disclosed. If a cross-colour component prediction mode is allowed, the luma block and the chroma block are partitioned into one or more luma leaf blocks and chroma leaf blocks. If a cross-colour component prediction mode is allowed, whether to enable an LM (Linear Model) mode for a target chroma leaf block is determined based on a first split type applied to an ancestor chroma node of the target chroma leaf block and a second split type applied to a corresponding ancestor luma node. According to another method, after the luma block and the chroma block are partitioned using different partition tress, determine whether one or more exception conditions to allow an LM for a target chroma leaf block are satisfied when the chroma partition tree uses a different split type, a different partition direction, or both from the luma partition tree.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor processing system including an overlay (OVL) shift measurement device. The OVL shift measurement device is configured to determine an OVL shift between a first wafer and a second wafer, where the second wafer overlies the first wafer. A photolithography device is configured to perform one or more photolithography processes on the second wafer. A controller is configured to perform an alignment process on the photolithography device according to the determined OVL shift. The photolithography device performs the one or more photolithography processes based on the OVL shift.

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

Abstract: A semiconductor device includes an integrated passive device coupled to a redistribution structure by a plurality of first bumps, and having a plurality of second bumps disposed opposite the plurality of first bumps, wherein the plurality of first and second bumps are thermally and/or electrically connected, and thus enable further thermal and/or electrical connections within or comprising the semiconductor device.

Abstract: A system and method utilize capacitance sensor data to identify cell events with single-cell resolution. The method identifies patterns in the sensor data related to events such as mitosis, migration-in to the sensor field, and migration-out. The system may include a processor co-located with the sensor to perform the pattern recognition. Further, microfluidic channels can be provided to direct cells to the sensors.

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

Abstract: A thermal ground plane (TGP) is disclosed. A TGP may include a first planar substrate member comprising copper and a second planar substrate member comprising a metal, wherein the first planar substrate member and the second planar substrate member enclose a working fluid. The TGP may include a first plurality of pillars disposed on an interior surface of the first planar substrate and a mesh layer disposed on the top of the first plurality of pillars, wherein the mesh layer comprises at least one of copper, polymer encapsulated with copper, or stainless steel encapsulated with copper. The TGP may also include a second plurality of pillars disposed on an interior surface of the second planar substrate member within an area defined by the perimeter of the second planar substrate member and the second plurality of pillars extend from the second planar substrate member to the mesh layer.

Abstract: Provided herein are compositions, systems, kits, and methods for treating nervous system injuries caused by trauma or neurodegeneration or aging in a subject by administering a CSPG or SOCS3 reduction peptide (CRP and SRP respectively), or a nucleic acid sequence encoding the CRP or SRP, wherein both the CRP and SRP comprise a cell membrane penetrating domain, and a lysosome targeting domain, and the CRP further comprises a chondroitin sulfate proteoglycan (CSPG) binding domain, and the SRP further comprises a suppressor of cytokine signaling-3 (SOCS3) binding domain.

Abstract: A semiconductor device includes a first substrate. The semiconductor device includes a plurality of metallization layers formed over the first substrate. The semiconductor device includes a plurality of via structures formed over the plurality of metallization layers. The semiconductor device includes a second substrate attached to the first substrate through the plurality of via structures. The semiconductor device includes a first conductive line disposed in a first one of the plurality of metallization layers. The first conductive line, extending along a first lateral direction, is connected to at least a first one of the plurality of via structures that is in electrical contact with a first through via structure of the second substrate, and to at least a second one of the plurality of via structures that is laterally offset from the first through via structure.

Abstract: A phone appliance and method of use are provided where the phone appliance can be used to make VoIP communications calls. In a preferred embodiment, the phone appliance includes an RF connection for connecting to a computer or other computing device for facilitating the placement of the VoIP communications calls. The phone appliance further includes a display or portal for depicting advertisements provided by various advertisers. The advertisements provided can be used to defray all or part of the cost associated with making VoIP communications calls. The portal can also be used to communicate with businesses for ordering products, such as ordering a pizza, and to perform various services, such as purchasing stocks. In an exemplary system, the phone appliance is used to transmit to a control center information related to the user of the phone appliance, such as interests and buying habits, and queries for receiving additional information for various advertised products and services.

Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.

Abstract: A thermal ground plane (TGP) is disclosed. A TGP may include a first planar substrate member comprising copper and a second planar substrate member comprising a metal, wherein the first planar substrate member and the second planar substrate member enclose a working fluid. The TGP may include a first plurality of pillars disposed on an interior surface of the first planar substrate and a mesh layer disposed on the top of the first plurality of pillars, wherein the mesh layer comprises at least one of copper, polymer encapsulated with copper, or stainless steel encapsulated with copper. The TGP may also include a second plurality of pillars disposed on an interior surface of the second planar substrate member within an area defined by the perimeter of the second planar substrate member and the second plurality of pillars extend from the second planar substrate member to the mesh layer.

Abstract: A method of forming a semiconductor device includes forming a first interconnect structure over a carrier; forming a thermal dissipation block over the carrier; forming metal posts over the first interconnect structure; attaching a first integrated circuit die over the first interconnect structure and the thermal dissipation block; removing the carrier; attaching a semiconductor package to the first interconnect structure and the thermal dissipation block using first electrical connectors and thermal dissipation connectors; and forming external electrical connectors, the external electrical connectors being configured to transmit each external electrical connection into the semiconductor device, the thermal dissipation block being electrically isolated from each external electrical connection.

Abstract: A phone appliance and method of use are provided where the phone appliance can be used to make VoIP communications calls. In a preferred embodiment, the phone appliance includes an RF connection for connecting to a computer or other computing device for facilitating the placement of the VoIP communications calls. The phone appliance further includes a display or portal for depicting advertisements provided by various advertisers. The advertisements provided can be used to defray all or part of the cost associated with making VoIP communications calls. The portal can also be used to communicate with businesses for ordering products. such as ordering a pizza, and to perform various services, such as purchasing stocks. In an exemplary system, the phone appliance is used to transmit to a control center information related to the user of the phone appliance, such as interests and buying habits, and queries for receiving additional information for various advertised products and services.