Abstract: A voltage controlled oscillator (VCO) includes a voltage controlled current source (VCCS), a negative resistance circuit (NRC), a first transformer, a second transformer, a first transistor and a second transistor. A current terminal of the VCCS receives a control voltage. First terminals of first and second current paths in the NRC are coupled to a current terminal of the VCCS. Primary sides of the first and the second transformers are respectively coupled to second terminals of the first and the second current paths. Secondary sides of the first and the second transformers are first and second output terminals of the VCO, respectively. First terminals of the first and the second transistor are respectively coupled to the secondary sides of the first and the second transformers. Control terminals of the first and the second transformers are respectively coupled to the primary sides of the first and the second transformers.

Abstract: A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

Abstract: A voltage controlled oscillator (VCO) includes a voltage controlled current source (VCCS), a negative resistance circuit (NRC), a first transformer, a second transformer, a first transistor and a second transistor. A current terminal of the VCCS receives a control voltage. First terminals of first and second current paths in the NRC are coupled to a current terminal of the VCCS. Primary sides of the first and the second transformers are respectively coupled to second terminals of the first and the second current paths. Secondary sides of the first and the second transformers are first and second output terminals of the VCO, respectively. First terminals of the first and the second transistor are respectively coupled to the secondary sides of the first and the second transformers. Control terminals of the first and the second transformers are respectively coupled to the primary sides of the first and the second transformers.

Abstract: A bust-mode clock and data recovery circuit using phase selecting technology is provided. In the data recovery circuit, a phase-locked loop (PLL) circuit is used for providing a plurality of fixed clock signals, each of which has a clock phase. An oversampling phase selecting circuit is coupled to the phase-locked loop circuit and used for detecting a data edge of a received data signal by using the clock signals and selects a clock phase to be locked according to the location of the data edge. A delay-locked loop (DLL) circuit is coupled to the phase-locked loop circuit and the oversampling phase selecting circuit, and used for comparing the data phase of the data signal with the clock phase of the selected clock signal, so as to delay the data phase of the data signal by a delay time until the data phase is locked as the clock phase.

Abstract: A robot-like electronic device changeable from a cubical or box profile to a robot profile includes a first body, two second bodies and a third body. The two second bodies are hinged to two sides of the first body through a swiveling beam. The third body is pivotally coupled on the bottom side of the first body. The first, second and third bodies can swivel relative to one another. The two second bodies and the third body can be coupled with the first body, to become a cubic or box. The two second bodies also may be swiveled outwards, like two arms of a robot. The third body can be swiveled 90 degrees relative to the first body and bent forwards like a foot, so that the first body can stand upright on a flat surface like a robot.

Abstract: A robot-like electronic device changeable from a cubical or box profile to a robot profile includes a first body, two second bodies and a third body. The two second bodies are hinged to two sides of the first body through a swiveling beam. The third body is pivotally coupled on the bottom side of the first body. The first, second and third bodies can swivel relative to one another. The two second bodies and the third body can be coupled with the first body, to become a cubic or box. The two second bodies also may be swiveled outwards, like two arms of a robot. The third body can be swiveled 90 degrees relative to the first body and bent forwards like a foot, so that the first body can stand upright on a flat surface like a robot.

Abstract: A digital adjustable chip oscillator comprises a voltage control oscillator, a reference voltage circuit, a voltage regulation circuit, a digital tuning circuit, a frequency detector and a programmable controller. The oscillator generates an oscillation signal and receives a control voltage and an operating voltage from the voltage regulation circuit and the reference voltage circuit to stabilize and adjust the frequency of oscillation signal. The digital tuning circuit receives a digital code stored in a programmable memory to adjust the control voltage. The frequency detector detects and compares the frequency of oscillation signal with a first and second frequency, wherein when the frequency of the oscillation signal lies between the first and second frequency, the frequency detector outputs a high voltage signal and otherwise the frequency detector outputs a low voltage signal. The programmable controller receives the high voltage signal to stop a programmable counter to acquire the digital code.

Abstract: A one-wire clock-skew compensating method and a circuit for the method are disclosed to solve the clock-skew problem in transmission of clock signals in a high-speed synchronous circuit such as of a CPU, hence the clock of a remote circuit and the clock input of the system can be accurately synchronized. The method is based on the principle of identical propagation delay on the forward and reverse paths at the two ends of one wire in transmission and receiving; a clock-deskew buffer composing a delay locked loop and a bidirectional buffer is provided in the front of the signal transmission end of the wire, while the other end of the wire has a bidirectional buffer too, hence signals are transmitted bidirectionally at the same time on the wire.

Abstract: A digital adjustable chip oscillator comprising: a voltage control oscillator generating an oscillation signal, receiving a control voltage to adjust the frequency of the oscillation signal, and receiving an operating voltage to stabilize the frequency of the oscillation signal; a reference voltage circuit generating a reference voltage; a voltage regulation circuit receiving the reference voltage and generating the operating voltage; a digital tuning circuit receiving a digital code to adjust the control voltage and receiving the operating voltage to stabilize the control voltage; a frequency detector receiving the oscillation signal, a first reference signal with a first frequency, and a second reference signal with a second frequency, wherein when the frequency of the oscillation signal lies between the first frequency and the second frequency, the frequency detector will output a high voltage comparison signal, otherwise the frequency detector will output a low voltage comparison signal; a programmable co

Abstract: A table includes a top supported on a frame which having two cone-shaped insertions. Two leg sets each include two legs with a connection member connected therebetween. Each of the connection members has a receiving member which receives the insertion which are allowed to be pivotable to adjust the position of the leg sets.

Abstract: A toothbrush consists of a cylindrical brush handle forming a toothpaste receiver having toothpaste therein, a brush rod provided with brush bristles and a guide passage therein, a turning end cap formed with a threaded rod extending into the toothpaste receiver and a squeezing block threadingly engaging the threaded rod in the toothpaste receiver. When the end cap is turned, the squeezing block may be actuated to move forward or backward such that the toothpaste may be squeezed toward the brush rod to overflow over the brush bristles through the guide passage. By opening a seal lid of the turning end cap, a general toothpaste tube can be squeezed so that the toothpaste refills the toothpaste receiver during refilling.

Abstract: A one-wire clock-skew compensating method and a circuit for the method are disclosed to solve the clock-skew problem in transmission of clock signals in a high-speed synchronous circuit such as of a CPU, hence the clock of a remote circuit and the clock input of the system can be accurately synchronized. The method is based on the principle of identical propagation delay on the forward and reverse paths at the two ends of one wire in transmission and receiving; a clock-deskew buffer composing a delay locked loop and a bidirectional buffer is provided in the front of the signal transmission end of the wire, while the other end of the wire has a bidirectional buffer too, hence signals are transmitted bidirectionally at the same time on the wire.

Abstract: A toothbrush with filling of toothpaste basically comprises a cylindrical toothpaste receiver having toothpaste therein, a toothbrush head with a guide passage therein, a turning end cap with a threaded rod and a squeezing block attaching to the threaded rod. When the end cap is turned, the squeezing block may be actuated to move forward or backward such that the toothpaste may be squeezed toward the toothbrush head to overflow over the bristles through the guide passage.

Abstract: The invention of the "high-frequency CMOS dual/multi modulus prescaler" is a new application in this field. Compared to other transistors which have CMOS technology, this invention has a greater potential for high frequency operations. Additionally, it has a low-power consumption property and can be easily integrated with CMOS technology. We propose a general construction of the prescaler which can be applied to dual-modulus prescaler. First, a divide-by-3/4 dual-modulus prescaler and a divide-by-4/5 one are presented. Consequently, a general dual-modulus prescaler is developed based on the same technique. Moreover, a general multi-modulus prescaler will also be achieved. The operating frequency can be up to 1 GHz for the proposed dual/multiple modulus prescalers which are fabricated in a 0.8-.mu.m SPDM CMOS technology.

Abstract: A divide-by-4/5 counter includes a half transparent register, a domino logic, a buffer, a divide-by-4 counter and a control circuit. The half transparent register includes first, second, and third NMOS and PMOS transistors and first and second inverters. The domino logic includes fourth PMOS and NMOS transistors and first and second switches. The buffer is connected to a drain of the fourth PMOS transistor for out putting a reference clock signal. The divide-by-4 counter includes two divide-by-2 counters to obtain a divide-by-2 clock signal and an output clock signal. The control circuit is connected to a control terminal of the second switch for outputting a control signal of the domino logic according to the divide-by-2 clock signal, the output clock signal and a divide-by-4/5 control signal.