Abstract: A multi-mixer system includes an amplifier module and a plurality of channels. The amplifier module is arranged for receiving signals from an antenna or antenna arrays to generate a plurality of radio frequency (RF) input signals. The plurality of channels are coupled to the amplifier module, wherein the plurality of channels receive the RF input signals, respectively, and each of the channels includes a mixer for mixing one of the RF input signals with a local oscillating signal to generate a mixed signal. In addition, at least one of the channels includes an interference reduction circuit positioned between the amplifier module and the mixer.

Abstract: A multi-mixer system includes an amplifier module and a plurality of channels. The amplifier module is arranged for receiving signals from an antenna or antenna arrays to generate a plurality of radio frequency (RF) input signals. The plurality of channels are coupled to the amplifier module, wherein the plurality of channels receive the RF input signals, respectively, and each of the channels includes a mixer for mixing one of the RF input signals with a local oscillating signal to generate a mixed signal. In addition, at least one of the channels includes an interference reduction circuit positioned between the amplifier module and the mixer.

Abstract: A multi-mixer system includes an amplifier module and a plurality of channels. The amplifier module is arranged for receiving signals from an antenna or antenna arrays to generate a plurality of radio frequency (RF) input signals. The plurality of channels are coupled to the amplifier module, wherein the plurality of channels receive the RF input signals, respectively, and each of the channels includes a mixer for mixing one of the RF input signals with a local oscillating signal to generate a mixed signal. In addition, at least one of the channels includes an interference reduction circuit positioned between the amplifier module and the mixer.

Abstract: A multi-mixer system includes an amplifier module and a plurality of channels. The amplifier module is arranged for receiving signals from an antenna or antenna arrays to generate a plurality of radio frequency (RF) input signals. The plurality of channels are coupled to the amplifier module, wherein the plurality of channels receive the RF input signals, respectively, and each of the channels includes a mixer for mixing one of the RF input signals with a local oscillating signal to generate a mixed signal. In addition, at least one of the channels includes an interference reduction circuit positioned between the amplifier module and the mixer.

Abstract: A receiver apparatus includes a receiver path and a blocker detection path. The receiver path includes a down-converting stage. The blocker detection path includes a sensing circuit and a blocker detection circuit. The sensing circuit is arranged to sense a received radio frequency signal which has not yet been processed by the down-converting stage and generate a sensed signal accordingly. The blocker detection circuit is arranged to detect existence of a blocker signal according to the sensed signal and generate a blocker detection result indicative of the existence of the blocker signal when receiving the sensed signal.

Abstract: A receiver apparatus includes a receiver path and a blocker detection path. The receiver path includes a down-converting stage. The blocker detection path includes a sensing circuit and a blocker detection circuit. The sensing circuit is arranged to sense a received radio frequency signal which has not yet been processed by the down-converting stage and generate a sensed signal accordingly. The blocker detection circuit is arranged to detect existence of a blocker signal according to the sensed signal and generate a blocker detection result indicative of the existence of the blocker signal when receiving the sensed signal.

Abstract: An exemplary embodiment of a full division duplex system comprises a receiver, a transmitter and an auxiliary circuit. The receiver receives an inbound RF signal of a first band to generate an inbound baseband signal, and the transmitter up converts an outbound baseband signal by an oscillation signal to generate an outbound RF signal of a second band for transmission. The auxiliary circuit calculates leakages from the outbound RF signal to generate a blocker replica, in which a LNA is coupled to a non-conductive coupling path extended from the input of receiver to collect leakages from the outbound RF signal to produce an induction signal. The induction signal is down converted to perform an adjustment, and thereafter up converted again to generate the blocker replica. In this way, the inbound baseband signal is generated from a subtraction of the inbound RF signal and the blocker replica.

Abstract: A direct conversion receiver and a DC offset cancellation method are provided. An RF module receives a transmission signal to generate an RF signal. A mixer converts the RF signal to a mixer output comprising baseband and imaginary parts. A filter module filters out the imaginary part of the mixer output and adjusts gain of the baseband part to generate a baseband signal. A calibrator performs a calibration to determine a mismatch value of the mixer. A static DC offset canceller provides a constant offset compensation according to the mismatch value; wherein the mismatch value is used to minimize component mismatching effects of the mixer.

Abstract: The instant invention relates to an apparatus and method for enhancing DC offset correction speed of a radio device. On the exemplary, the apparatus includes one or two-stage signal-processing units and a controller. Each signal-processing unit has a baseband filter, a gain stage and a DC offset correction (DCOC) loop applied on the gain stage. A connection direction of an electrode terminal of a capacitor of the baseband filter is capable of being switched by the controller to process a pre-charge or a discharge phases thereby adjusting a bandwidth of the baseband filter to be either a normal operational bandwidth or wider than the normal operational bandwidth for rapidly setting time of the baseband filter.

Abstract: A steering and mixing module comprises a double balanced switch quad and a steering quad. The double balanced switch quad comprises a first output pair, and the first output pair is coupled to a first load stage. The steering quad comprises a second output pair, and the second output pair is coupled to a second load stage. The double balanced switch quad and the steering quad share an input pair.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.

Abstract: A converting/steering device has a normal mode and a calibration mode. The converting/steering device includes a merged mixer/VGA and a mode controller. The merged mixer/VGA has a mixing stage and an amplifying stage. In the normal mode, the mode controller deactivates the mixing stage of the merged mixer/VGA, and the device operates as an RF VGA. In the calibration mode, the mode controller activates the mixing stage of the merged mixer/VGA and passes a local oscillator signal to the mixing stage, so that the device operates as a down-mixer.

Abstract: A steering and mixing module comprises a double balanced switch quad and a steering quad. The double balanced switch quad comprises a first output pair, and the first output pair is coupled to a first load stage. The steering quad comprises a second output pair, and the second output pair is coupled to a second load stage. The double balanced switch quad and the steering quad share an input pair.

Abstract: An exemplary embodiment of a full division duplex system comprises a receiver, a transmitter and an auxiliary circuit. The receiver receives an inbound RF signal of a first band to generate an inbound baseband signal, and the transmitter up converts an outbound baseband signal by an oscillation signal to generate an outbound RF signal of a second band for transmission. The auxiliary circuit calculates leakages from the outbound RF signal to generate a blocker replica, in which a LNA is coupled to a non-conductive coupling path extended from the input of receiver to collect leakages from the outbound RF signal to produce an induction signal. The induction signal is down converted to perform an adjustment, and thereafter up converted again to generate the blocker replica. In this way, the inbound baseband signal is generated from a subtraction of the inbound RF signal and the blocker replica.

Abstract: An exemplary embodiment of a full division duplex system comprises a receiver, a transmitter and an auxiliary circuit. The receiver receives an inbound RF signal of a first band to generate an inbound baseband signal, and the transmitter up converts an outbound baseband signal by an oscillation signal to generate an outbound RF signal of a second band for transmission. The auxiliary circuit calculates leakages from the outbound RF signal to generate a blocker replica, in which a LNA is coupled to a non-conductive coupling path extended from the input of receiver to collect leakages from the outbound RF signal to produce an induction signal. The induction signal is down converted to perform an adjustment, and thereafter up converted again to generate the blocker replica. In this way, the inbound baseband signal is generated from a subtraction of the inbound RF signal and the blocker replica.

Abstract: A direct conversion receiver and a DC offset cancellation method are provided. An RF module receives a transmission signal to generate an RF signal. A mixer converts the RF signal to a mixer output comprising baseband and imaginary parts. A filter module filters out the imaginary part of the mixer output and adjusts gain of the baseband part to generate a baseband signal. A calibrator performs a calibration to determine a mismatch value of the mixer. A static DC offset canceller provides a constant offset compensation according to the mismatch value; wherein the mismatch value is used to minimize component mismatching effects of the mixer.

Abstract: An exemplary embodiment of a full division duplex system comprises a receiver, a transmitter and an auxiliary circuit. The receiver receives an inbound RF signal of a first band to generate an inbound baseband signal, and the transmitter up converts an outbound baseband signal by an oscillation signal to generate an outbound RF signal of a second band for transmission. The auxiliary circuit calculates leakages from the outbound RF signal to generate a blocker replica, in which a LNA is coupled to a non-conductive coupling path extended from the input of receiver to collect leakages from the outbound RF signal to produce an induction signal. The induction signal is down converted to perform an adjustment, and thereafter up converted again to generate the blocker replica. In this way, the inbound baseband signal is generated from a subtraction of the inbound RF signal and the blocker replica.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.

Abstract: A mixer and calibration method thereof are provided. A direct conversion receiver comprises a differential loading pair utilizing at least one binary weighted resistor. The binary weighted resistor is adjustable to provide a resistance linear to a digital code, comprising a fixed resistor and an adjustable resistor cascaded to the fixed resistor in parallel. Every increment of the digital code induces an equal increment of the resistance. The magnitude of every incremental resistance is below a negligible ratio of the fixed resistor.

Abstract: A tuning circuit for tuning an active filter includes a resistor-capacitor circuit comprising a variable capacitor and a resistor equivalent to a first resistor and a second resistor serially connected to the first resistor, a voltage generator for providing a constant reference voltage to the first resistor, a current replicating unit for replicating a current based on the constant reference voltage, a comparator for comparing a charging voltage as the current is charging a variable capacitor with the constant reference voltage, a counter for counting a number of cycles of a clock signal until the charging voltage reaches the constant reference voltage, a adjustment unit for calibrating a capacitance of the variable capacitor based on the number of cycles of a clock signal and a target count value associated with a predetermined RC time constant.