Abstract: A method of forming a semiconductor assembly includes forming a set of through-silicon vias in a carrier wafer, where a layer of the carrier wafer includes integrated devices. A die is coupled to a top surface of the carrier wafer including the set of through-silicon vias using hybrid bonding. One or more connection layers of the die are coupled to one or more of the through-silicon vias and coupled to one or more of the integrated devices. A second wafer is coupled to a top surface of the die. An amount is removed from a bottom surface of the carrier wafer that is parallel to and opposite to the top surface of the carrier wafer to reveal a conductive portion of at least one of the through-silicon vias.

Abstract: Embodiments of the present disclosure generally relate to planarization of surfaces on substrates and on layers formed on substrates. More specifically, embodiments of the present disclosure relate to planarization of surfaces on substrates for advanced packaging applications, such as surfaces of polymeric material layers. In one implementation, the method includes mechanically grinding a substrate surface against a polishing surface in the presence of a grinding slurry during a first polishing process to remove a portion of a material formed on the substrate; and then chemically mechanically polishing the substrate surface against the polishing surface in the presence of a polishing slurry during a second polishing process to reduce any roughness or unevenness caused by the first polishing process.

Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

Abstract: A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.

Abstract: Apparatuses, systems and methods for efficiently generating a package substrate. A semiconductor fabrication process (or process) fabricates each of a first glass package substrate and a second glass package substrate with a redistribution layer on a single side of a respective glass wafer. The process flips the second glass package substrate upside down and connects the glass wafers of the first and second glass package substrates together using a wafer bonding technique. In some implementations, the process uses copper-based wafer bonding. The resulting bonding between the two glass wafers contains no air gap, no underfill, and no solder bumps. Afterward, the side of the first glass package substrate opposite the glass wafer is connected to at least one integrated circuit. Additionally, the side of the second glass package substrate opposite the glass wafer is connected to a component on the motherboard through pads on the motherboard.

Abstract: The present disclosure relates to thin-form-factor semiconductor packages with integrated electromagnetic interference (“EMI”) shields and methods for forming the same. The packages described herein may be utilized to form high-density semiconductor devices. In certain embodiments, a silicon substrate is laser ablated to include one or more cavities and a plurality of vias surrounding the cavities. One or more semiconductor dies may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. A plurality of conductive interconnections are formed within the vias and may have contact points redistributed to desired surfaces of the die-embedded substrate assembly. Thereafter, an EMI shield is plated onto a surface of the die-embedded substrate assembly and connected to ground by at least one of the one or more conductive interconnections. The die-embedded substrate assembly may then be singulated and/or integrated with another semiconductor device.

Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.

Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.

Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

Abstract: Methods for forming circuit boards and circuit boards using an adhesion layer are described. A substrate with two surfaces is exposed to a bifunctional organic compound to form an adhesion layer on the first substrate surface. A resin layer is then deposited on the adhesion layer and the exposed substrate surfaces. Portions of the resin layer may be removed to expose metal pads for contacts.

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.

Abstract: The present disclosure relates to thin-form-factor semiconductor packages with integrated electromagnetic interference (“EMI”) shields and methods for forming the same. The packages described herein may be utilized to form high-density semiconductor devices. In certain embodiments, a silicon substrate is laser ablated to include one or more cavities and a plurality of vias surrounding the cavities. One or more semiconductor dies may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. A plurality of conductive interconnections are formed within the vias and may have contact points redistributed to desired surfaces of the die-embedded substrate assembly. Thereafter, an EMI shield is plated onto a surface of the die-embedded substrate assembly and connected to ground by at least one of the one or more conductive interconnections. The die-embedded substrate assembly may then be singulated and/or integrated with another semiconductor device.

Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.

Abstract: Methods for forming circuit boards and circuit boards using an adhesion layer are described. A substrate with two surfaces is exposed to a bifunctional organic compound to form an adhesion layer on the first substrate surface. A resin layer is then deposited on the adhesion layer and the exposed substrate surfaces. Portions of the resin layer may be removed to expose metal pads for contacts.

Abstract: A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer.

Abstract: An imprint lithography stamp includes a stamp body having a patterned surface and formed from a fluorinated ethylene propylene copolymer. The imprint lithography stamp further includes a backing plate with a plurality of through-holes with portions of the stamp body extending into the through-holes to adhere the stamp body to the backing plate. The patterned surface of the stamp body has a plurality of protrusions extending from the stamp body, which are used to form high aspect ratio features at high processing temperatures. A mold design for forming the imprint lithography stamp and an injection molding process for forming the imprint lithography stamp are also provided.