Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

Abstract: Embodiments of the present disclosure generally relate to planarization of surfaces on substrates and on layers formed on substrates. More specifically, embodiments of the present disclosure relate to planarization of surfaces on substrates for advanced packaging applications, such as surfaces of polymeric material layers. In one implementation, the method includes mechanically grinding a substrate surface against a polishing surface in the presence of a grinding slurry during a first polishing process to remove a portion of a material formed on the substrate; and then chemically mechanically polishing the substrate surface against the polishing surface in the presence of a polishing slurry during a second polishing process to reduce any roughness or unevenness caused by the first polishing process.

Abstract: The present disclosure generally relates to methods of micro-imprinting panels or substrates for advanced packaging applications. A redistribution layer comprising an epoxy material is deposited on a substrate layer and imprinted with a stamp to form an epoxy substrate patterned with a plurality of vias. The stamp is removed from the epoxy substrate, and the epoxy substrate is optionally etched with a plasma comprising oxygen to prevent the redistribution layer from becoming flowable when cured. A capping layer may optionally be deposited on the surface of the epoxy substrate.

Abstract: A method and apparatus for forming a plurality of vias in panels for advanced packaging applications is disclosed, according to one embodiment. A redistribution layer is deposited on a substrate layer. The redistribution layer may be deposited using a spin coating process, a spray coating process, a drop coating process, or lamination. The redistribution layer is then micro-imprinted using a stamp inside a chamber. The redistribution layer and the stamp are then baked inside the chamber. The stamp is removed from the redistribution layer to form a plurality of vias in the redistribution layer. Excess residue built-up on the redistribution layer may be removed using a descumming process. A residual thickness layer disposed between the bottom of each of the plurality of vias and the top of the substrate layer may have thickness of less than about 1 ?m.