Patents by Inventor Chirag Gupta
Chirag Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120825Abstract: A drive system suitable for motors and the like employs bidirectional FETs with active gate current sourcing and sinking to eliminate series diode losses. In one embodiment, the bidirectional FETs have floating field plates that can be dynamically biased according to device polarity.Type: ApplicationFiled: September 21, 2023Publication date: April 11, 2024Inventors: Chirag Gupta, Shubhra S. Pasayat, Daniel Ludois
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Patent number: 11936638Abstract: Methods, media, and systems for facilitating inter-application communications between a web platform and a remote application computing device are disclosed such that a link protocol agent associated with the web platform processes an authentication request based on which a temporary connection resource locator is provided. A connection is then established at the resource locator and maintained for a period of time. Payloads and acknowledgements are exchanged in the established connection. The connection is capable of being established across a firewall.Type: GrantFiled: June 28, 2020Date of Patent: March 19, 2024Assignee: Salesforce Inc.Inventors: Ankur Oberoi, Abhishek Mahanti, Helen Wei Zeng, Serguei Mourachov, Chirag Gupta, Saurabh Sahni
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Publication number: 20240063340Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.Type: ApplicationFiled: September 10, 2020Publication date: February 22, 2024Applicants: The Regents of the University of California, The Regents of the University of CaliforniaInventors: Stacia Keller, Umesh K. Mishra, Shubhra Pasayat, Chirag Gupta
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Publication number: 20230409296Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.Type: ApplicationFiled: August 29, 2023Publication date: December 21, 2023Applicant: The MathWorks, Inc.Inventors: Huanhuan Xu, Partha Biswas, Madhav Rajan, Sherman Braganza, Chirag Gupta, Neha Pal, Radhey Shyam Meena
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Patent number: 11782682Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.Type: GrantFiled: July 13, 2021Date of Patent: October 10, 2023Assignee: The Math Works, Inc.Inventors: Huanhuan Xu, Partha Biswas, Madhav Rajan, Sherman Braganza, Chirag Gupta, Neha Pal, Radhey Shyam Meena
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Patent number: 11588096Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.Type: GrantFiled: April 11, 2017Date of Patent: February 21, 2023Assignee: The Regents of the University of CaliforniaInventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
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Publication number: 20230021771Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.Type: ApplicationFiled: July 13, 2021Publication date: January 26, 2023Applicant: The MathWorks, Inc.Inventors: Huanhuan Xu, Partha Biswas, Madhav Rajan, Sherman Braganza, Chirag Gupta, Neha Pal, Radhey Shyam Meena
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Publication number: 20220417229Abstract: Techniques are disclosed for time constrained electronic request evaluation. A server system receives, from a computing device, a request submitted via an account, including a first set of characteristics associated with the request. The system executes a first machine-learning model to determine a first risk score for the request by inputting the first set of characteristics into the first model. The system generates an initial authentication decision for the request based on the first score and sends the decision to the device. The system executes a second, different machine-learning model to determine a second risk score for the request, by inputting the first set of characteristics and a second, different set of characteristics associated with the account into the second model. Based on the second score, the system determines a final authentication decision. The disclosed techniques may advantageously improve computer security and operations via identification of malicious electronic requests.Type: ApplicationFiled: August 11, 2021Publication date: December 29, 2022Inventors: Vishal Sood, Yegya Narayanan Gopala Krishnan, Sudhindra Murthy, Vidya Sagar Durga, Chirag Gupta
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Publication number: 20210399096Abstract: Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.Type: ApplicationFiled: November 7, 2019Publication date: December 23, 2021Applicant: The Regents of the University of CaliforniaInventors: Umesh K. Mishra, Stacia Keller, Elaheh Ahmadi, Chirag Gupta, Yusuke Tsukada
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Publication number: 20200412708Abstract: Methods, media, and systems for facilitating inter-application communications between a web platform and a remote application computing device are disclosed such that a link protocol agent associated with the web platform processes an authentication request based on which a temporary connection resource locator is provided. A connection is then established at the resource locator and maintained for a period of time. Payloads and acknowledgements are exchanged in the established connection. The connection is capable of being established across a firewall.Type: ApplicationFiled: June 28, 2020Publication date: December 31, 2020Inventors: Ankur Oberoi, Abhishek Mahanti, Helen Wei Zeng, Serguei Mourachov, Chirag Gupta, Saurabh Sahni
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Patent number: 10635682Abstract: Analyzing log data. The method includes obtaining a first bucket of a log data. The first bucket of log data includes a plurality of log lines. The method further includes analyzing the first bucket of log data to identify different sets of similar log lines. The method further includes providing to a user in a user interface one or more summaries of the different sets of similar lines. The summary comprises at least one user selectable indicator representing differences in log lines in a set of similar log lines that when selected by a user in the user interface reveals specific differences in the log lines in the set of similar log lines.Type: GrantFiled: April 15, 2016Date of Patent: April 28, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Srivatsan Parthasarathy, Rohit Bhardwaj, Chirag Gupta, Vipul Malhotra, Evan Herschel Brodie Hissey
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Publication number: 20190181329Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.Type: ApplicationFiled: April 11, 2017Publication date: June 13, 2019Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
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Patent number: 10312361Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.Type: GrantFiled: November 4, 2016Date of Patent: June 4, 2019Assignee: The Regents of the University of CaliforniaInventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
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Publication number: 20180330275Abstract: Generally discussed herein are devices, systems, and methods for machine-learning. A method may include training, based on sparseness constraints and using a first device, a sparse matrix, prototype vectors, prototype labels, and corresponding prototype score vectors, simultaneously, storing the sparse matrix, prototype vectors, and prototype labels on a random-access memory (RAM) of a second device, projecting, using the second device, a prediction vector of a second dimensional space to the first dimensional space, the first dimensional space less than the second dimensional space, determining whether the projected prediction vector is closer to the one or more first prototype vectors or the one or more second prototype vectors, and determining a prediction by identifying the which prediction outcome the projected prediction vector is closer to.Type: ApplicationFiled: June 15, 2017Publication date: November 15, 2018Inventors: Prateek Jain, Chirag Gupta, Arun Sai Suggala, Ankit Goyal, Harshavardhan Simhadri
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Publication number: 20170169080Abstract: Analyzing log data. The method includes obtaining a first bucket of a log data. The first bucket of log data includes a plurality of log lines. The method further includes analyzing the first bucket of log data to identify different sets of similar log lines. The method further includes providing to a user in a user interface one or more summaries of the different sets of similar lines. The summary comprises at least one user selectable indicator representing differences in log lines in a set of similar log lines that when selected by a user in the user interface reveals specific differences in the log lines in the set of similar log lines.Type: ApplicationFiled: April 15, 2016Publication date: June 15, 2017Inventors: Srivatsan Parthasarathy, Rohit Bhardwaj, Chirag Gupta, Vipul Malhotra, Evan Herschel Brodie Hissey
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Publication number: 20170125574Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.Type: ApplicationFiled: November 4, 2016Publication date: May 4, 2017Applicants: The Regents of the University of Calfornia, Arizona Board of Regents on Behalf of Arizona State UniversityInventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
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Patent number: 9164687Abstract: A system and method for deduplicating messages is provided. Duplicate copies of messages are excluded from a set of deduplicated messages. The set of deduplicated messages can then be sampled to obtain a sample set usable for ensuring compliance according to a set of rules. One method for deduplicating messages involves receiving a message, determining whether the message is a duplicate copy, and adding the message to the set of deduplicated messages, if it is determined that the message is not a duplicate copy.Type: GrantFiled: January 14, 2011Date of Patent: October 20, 2015Assignee: Symantec CorporationInventors: Neel Atulkumar Bhatt, Sunil Sharad Panse, Chirag Gupta, Siddharth Ranoj Barman, Shankar Nabhaji Hundekar
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Publication number: 20140324936Abstract: Processors and methods for solving mathematical equations are disclosed herein. An embodiment of the processor includes a hardware device that calculates coefficients based on a mathematical operation that is to be performed. An indexing device transmits the coefficients to and from a look up table. A hardware multiplier multiplies certain coefficients by the derivative of a function related to the mathematical operation. A hardware adder adds a first coefficient to the product of a second coefficient and the first order derivative of the function.Type: ApplicationFiled: August 20, 2013Publication date: October 30, 2014Applicant: Texas Instruments IncorporatedInventors: Tessarolo Alexander, Chirag Gupta