Patents by Inventor Chirag Gupta

Chirag Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120825
    Abstract: A drive system suitable for motors and the like employs bidirectional FETs with active gate current sourcing and sinking to eliminate series diode losses. In one embodiment, the bidirectional FETs have floating field plates that can be dynamically biased according to device polarity.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 11, 2024
    Inventors: Chirag Gupta, Shubhra S. Pasayat, Daniel Ludois
  • Patent number: 11936638
    Abstract: Methods, media, and systems for facilitating inter-application communications between a web platform and a remote application computing device are disclosed such that a link protocol agent associated with the web platform processes an authentication request based on which a temporary connection resource locator is provided. A connection is then established at the resource locator and maintained for a period of time. Payloads and acknowledgements are exchanged in the established connection. The connection is capable of being established across a firewall.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: March 19, 2024
    Assignee: Salesforce Inc.
    Inventors: Ankur Oberoi, Abhishek Mahanti, Helen Wei Zeng, Serguei Mourachov, Chirag Gupta, Saurabh Sahni
  • Publication number: 20240063340
    Abstract: The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.
    Type: Application
    Filed: September 10, 2020
    Publication date: February 22, 2024
    Applicants: The Regents of the University of California, The Regents of the University of California
    Inventors: Stacia Keller, Umesh K. Mishra, Shubhra Pasayat, Chirag Gupta
  • Publication number: 20230409296
    Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.
    Type: Application
    Filed: August 29, 2023
    Publication date: December 21, 2023
    Applicant: The MathWorks, Inc.
    Inventors: Huanhuan Xu, Partha Biswas, Madhav Rajan, Sherman Braganza, Chirag Gupta, Neha Pal, Radhey Shyam Meena
  • Patent number: 11782682
    Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: October 10, 2023
    Assignee: The Math Works, Inc.
    Inventors: Huanhuan Xu, Partha Biswas, Madhav Rajan, Sherman Braganza, Chirag Gupta, Neha Pal, Radhey Shyam Meena
  • Patent number: 11588096
    Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 21, 2023
    Assignee: The Regents of the University of California
    Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
  • Publication number: 20230021771
    Abstract: Systems and methods for providing metric data for patterns in a modeling environment are disclosed. In some aspects, contexts for generating metric data for a pattern are constructed. The pattern represents one or more computations executable in the modeling environment and associated with operation or behavior of a real-world system. The contexts include information about the pattern. The metric data is associated with one or more objectives with which the use of the pattern is associated. Code for the pattern for each context is generated. Metric data is generated for the pattern and under each context. The metric data of the pattern under each context is associated with the objectives. The metric data and the association are stored for use in providing information about or based on the metric data when the pattern is to be or is used in a model representing the real-world system.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 26, 2023
    Applicant: The MathWorks, Inc.
    Inventors: Huanhuan Xu, Partha Biswas, Madhav Rajan, Sherman Braganza, Chirag Gupta, Neha Pal, Radhey Shyam Meena
  • Publication number: 20220417229
    Abstract: Techniques are disclosed for time constrained electronic request evaluation. A server system receives, from a computing device, a request submitted via an account, including a first set of characteristics associated with the request. The system executes a first machine-learning model to determine a first risk score for the request by inputting the first set of characteristics into the first model. The system generates an initial authentication decision for the request based on the first score and sends the decision to the device. The system executes a second, different machine-learning model to determine a second risk score for the request, by inputting the first set of characteristics and a second, different set of characteristics associated with the account into the second model. Based on the second score, the system determines a final authentication decision. The disclosed techniques may advantageously improve computer security and operations via identification of malicious electronic requests.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 29, 2022
    Inventors: Vishal Sood, Yegya Narayanan Gopala Krishnan, Sudhindra Murthy, Vidya Sagar Durga, Chirag Gupta
  • Publication number: 20210399096
    Abstract: Strain is used to enhance the properties of p- and n-materials so as to improve the performance of III-N electronic and optoelectronic devices. In one example, transistor devices include a channel aligned along uniaxially strained or relaxed directions of the III-nitride material in the channel. Strain is introduced using buffer layers or source and drain regions of different composition.
    Type: Application
    Filed: November 7, 2019
    Publication date: December 23, 2021
    Applicant: The Regents of the University of California
    Inventors: Umesh K. Mishra, Stacia Keller, Elaheh Ahmadi, Chirag Gupta, Yusuke Tsukada
  • Publication number: 20200412708
    Abstract: Methods, media, and systems for facilitating inter-application communications between a web platform and a remote application computing device are disclosed such that a link protocol agent associated with the web platform processes an authentication request based on which a temporary connection resource locator is provided. A connection is then established at the resource locator and maintained for a period of time. Payloads and acknowledgements are exchanged in the established connection. The connection is capable of being established across a firewall.
    Type: Application
    Filed: June 28, 2020
    Publication date: December 31, 2020
    Inventors: Ankur Oberoi, Abhishek Mahanti, Helen Wei Zeng, Serguei Mourachov, Chirag Gupta, Saurabh Sahni
  • Patent number: 10635682
    Abstract: Analyzing log data. The method includes obtaining a first bucket of a log data. The first bucket of log data includes a plurality of log lines. The method further includes analyzing the first bucket of log data to identify different sets of similar log lines. The method further includes providing to a user in a user interface one or more summaries of the different sets of similar lines. The summary comprises at least one user selectable indicator representing differences in log lines in a set of similar log lines that when selected by a user in the user interface reveals specific differences in the log lines in the set of similar log lines.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 28, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Srivatsan Parthasarathy, Rohit Bhardwaj, Chirag Gupta, Vipul Malhotra, Evan Herschel Brodie Hissey
  • Publication number: 20190181329
    Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.
    Type: Application
    Filed: April 11, 2017
    Publication date: June 13, 2019
    Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
  • Patent number: 10312361
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 4, 2019
    Assignee: The Regents of the University of California
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • Publication number: 20180330275
    Abstract: Generally discussed herein are devices, systems, and methods for machine-learning. A method may include training, based on sparseness constraints and using a first device, a sparse matrix, prototype vectors, prototype labels, and corresponding prototype score vectors, simultaneously, storing the sparse matrix, prototype vectors, and prototype labels on a random-access memory (RAM) of a second device, projecting, using the second device, a prediction vector of a second dimensional space to the first dimensional space, the first dimensional space less than the second dimensional space, determining whether the projected prediction vector is closer to the one or more first prototype vectors or the one or more second prototype vectors, and determining a prediction by identifying the which prediction outcome the projected prediction vector is closer to.
    Type: Application
    Filed: June 15, 2017
    Publication date: November 15, 2018
    Inventors: Prateek Jain, Chirag Gupta, Arun Sai Suggala, Ankit Goyal, Harshavardhan Simhadri
  • Publication number: 20170169080
    Abstract: Analyzing log data. The method includes obtaining a first bucket of a log data. The first bucket of log data includes a plurality of log lines. The method further includes analyzing the first bucket of log data to identify different sets of similar log lines. The method further includes providing to a user in a user interface one or more summaries of the different sets of similar lines. The summary comprises at least one user selectable indicator representing differences in log lines in a set of similar log lines that when selected by a user in the user interface reveals specific differences in the log lines in the set of similar log lines.
    Type: Application
    Filed: April 15, 2016
    Publication date: June 15, 2017
    Inventors: Srivatsan Parthasarathy, Rohit Bhardwaj, Chirag Gupta, Vipul Malhotra, Evan Herschel Brodie Hissey
  • Publication number: 20170125574
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 4, 2017
    Applicants: The Regents of the University of Calfornia, Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • Patent number: 9164687
    Abstract: A system and method for deduplicating messages is provided. Duplicate copies of messages are excluded from a set of deduplicated messages. The set of deduplicated messages can then be sampled to obtain a sample set usable for ensuring compliance according to a set of rules. One method for deduplicating messages involves receiving a message, determining whether the message is a duplicate copy, and adding the message to the set of deduplicated messages, if it is determined that the message is not a duplicate copy.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: October 20, 2015
    Assignee: Symantec Corporation
    Inventors: Neel Atulkumar Bhatt, Sunil Sharad Panse, Chirag Gupta, Siddharth Ranoj Barman, Shankar Nabhaji Hundekar
  • Publication number: 20140324936
    Abstract: Processors and methods for solving mathematical equations are disclosed herein. An embodiment of the processor includes a hardware device that calculates coefficients based on a mathematical operation that is to be performed. An indexing device transmits the coefficients to and from a look up table. A hardware multiplier multiplies certain coefficients by the derivative of a function related to the mathematical operation. A hardware adder adds a first coefficient to the product of a second coefficient and the first order derivative of the function.
    Type: Application
    Filed: August 20, 2013
    Publication date: October 30, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Tessarolo Alexander, Chirag Gupta