Patents by Inventor Chirag Gupta

Chirag Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190181329
    Abstract: An optoelectronic or electronic device structure, including an active region on or above a polar substrate, wherein the active region comprises a polar p region. The device structure further includes a hole supply region on or above the active region. Holes in the hole supply region are driven by a field into the active region, the field arising at least in part due to a piezoelectric and/or spontaneous polarization field generated by a composition and grading of the active region.
    Type: Application
    Filed: April 11, 2017
    Publication date: June 13, 2019
    Inventors: Yuuki Enatsu, Chirag Gupta, Stacia Keller, Umesh K. Mishra, Anchal Agarwal
  • Patent number: 10312361
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 4, 2019
    Assignee: The Regents of the University of California
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • Publication number: 20180330275
    Abstract: Generally discussed herein are devices, systems, and methods for machine-learning. A method may include training, based on sparseness constraints and using a first device, a sparse matrix, prototype vectors, prototype labels, and corresponding prototype score vectors, simultaneously, storing the sparse matrix, prototype vectors, and prototype labels on a random-access memory (RAM) of a second device, projecting, using the second device, a prediction vector of a second dimensional space to the first dimensional space, the first dimensional space less than the second dimensional space, determining whether the projected prediction vector is closer to the one or more first prototype vectors or the one or more second prototype vectors, and determining a prediction by identifying the which prediction outcome the projected prediction vector is closer to.
    Type: Application
    Filed: June 15, 2017
    Publication date: November 15, 2018
    Inventors: Prateek Jain, Chirag Gupta, Arun Sai Suggala, Ankit Goyal, Harshavardhan Simhadri
  • Publication number: 20170169080
    Abstract: Analyzing log data. The method includes obtaining a first bucket of a log data. The first bucket of log data includes a plurality of log lines. The method further includes analyzing the first bucket of log data to identify different sets of similar log lines. The method further includes providing to a user in a user interface one or more summaries of the different sets of similar lines. The summary comprises at least one user selectable indicator representing differences in log lines in a set of similar log lines that when selected by a user in the user interface reveals specific differences in the log lines in the set of similar log lines.
    Type: Application
    Filed: April 15, 2016
    Publication date: June 15, 2017
    Inventors: Srivatsan Parthasarathy, Rohit Bhardwaj, Chirag Gupta, Vipul Malhotra, Evan Herschel Brodie Hissey
  • Publication number: 20170125574
    Abstract: Trenched vertical power field-effect transistors with improved on-resistance and/or breakdown voltage are fabricated. In one or more embodiments, the modulation of the current flow of the transistor occurs in the lateral channel, whereas the voltage is predominantly held in the vertical direction in the off-state. When the device is in the on-state, the current is channeled through an aperture in a current-blocking region after it flows under a gate region into the drift region. In another embodiment, a novel vertical power low-loss semiconductor multi-junction device in III-nitride and non-III-nitride material system is provided. One or more multi-junction device embodiments aim at providing enhancement mode (normally-off) operation alongside ultra-low on resistance and high breakdown voltage.
    Type: Application
    Filed: November 4, 2016
    Publication date: May 4, 2017
    Applicants: The Regents of the University of Calfornia, Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Srabanti Chowdhury, Jeonghee Kim, Chirag Gupta, Stacia Keller, Silvia H. Chan, Umesh K. Mishra
  • Patent number: 9164687
    Abstract: A system and method for deduplicating messages is provided. Duplicate copies of messages are excluded from a set of deduplicated messages. The set of deduplicated messages can then be sampled to obtain a sample set usable for ensuring compliance according to a set of rules. One method for deduplicating messages involves receiving a message, determining whether the message is a duplicate copy, and adding the message to the set of deduplicated messages, if it is determined that the message is not a duplicate copy.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: October 20, 2015
    Assignee: Symantec Corporation
    Inventors: Neel Atulkumar Bhatt, Sunil Sharad Panse, Chirag Gupta, Siddharth Ranoj Barman, Shankar Nabhaji Hundekar
  • Publication number: 20140324936
    Abstract: Processors and methods for solving mathematical equations are disclosed herein. An embodiment of the processor includes a hardware device that calculates coefficients based on a mathematical operation that is to be performed. An indexing device transmits the coefficients to and from a look up table. A hardware multiplier multiplies certain coefficients by the derivative of a function related to the mathematical operation. A hardware adder adds a first coefficient to the product of a second coefficient and the first order derivative of the function.
    Type: Application
    Filed: August 20, 2013
    Publication date: October 30, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Tessarolo Alexander, Chirag Gupta