Patents by Inventor Chirag S. Patel

Chirag S. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098032
    Abstract: Systems and methods for guided vehicle matching are disclosed. In order to generate vehicle recommendations for a user of an electronic vehicle listing service, a plurality of vehicle-related lifestyle options are presented to the user, and a user selection received. Additional data regarding the user's vehicle preferences, requirements, or usage may be obtained. Based upon such information, a set of example vehicles is generated and presented to the user. Each example vehicle has characteristics representing a plurality of other vehicles. Based upon user ratings or selections of at least some of the example vehicles, a plurality of vehicle recommendations for specific available vehicles are generated and presented to the user. In some embodiments, further user interaction with such recommendations is used to refine the vehicle recommendations and identify additional vehicle recommendations.
    Type: Application
    Filed: August 5, 2019
    Publication date: March 26, 2020
    Inventors: Barbara August, Leena Ansari, Bree J. Radloff, William Ryan Page, David Matthew Krell, Michael N. Morgan, Sainaga Srikantham, Samantha Volker, Addhyan Pandey, Michael D. Heinley, Chirag S. Patel, Greg Heidorn, Seth Goldberg, Dennis R. Sherman
  • Publication number: 20200090244
    Abstract: Systems and methods for providing information regarding vehicle inventory availability to users of an information system are disclosed. When generating a vehicle data page for a particular vehicle at a particular location, the information system may generate an expected duration of availability of the vehicle as a prediction of the time between listing and sale of the vehicle. When the expected duration of availability is below a threshold, a status indicator may be generated and added to the vehicle data page to alert users that the vehicle is expected to remain available for only a short period of time. An estimate of time remaining for the vehicle may also be generated and presented to users as part of the vehicle data page.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Inventors: Addhyan Pandey, Sandeep Kandekar, Krishna Anisetty, Alicia A. Nevels, Sunita Negi, Salin Thomas, Srilakshmi Rayapeddi, Nikhil Patel, Chirag S. Patel, David Matthew Krell, Ramesh Jankampet, Audrey Salerno, Jennifer Wylie
  • Patent number: 9159616
    Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: October 13, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harvey Hamel, John Ulrich Knickerbocker, Samuel McKnight, Chirag S. Patel
  • Patent number: 9119164
    Abstract: An access point generates beacons at different power levels at different times to provide an acceptable tradeoff between coverage area associated with the beacons and outage experienced at nearby access terminals. For example, a femto access point may transmit beacons at a relatively low power for a relatively long period of time to reduce interference at nearby access terminals that are being served by a macro access point. The femto access point may then transmit beacons at a relatively high power for a relatively short period of time to enable nearby access terminals to receive the beacons. Also, a given transmit chain may be used to provide frequency hopping of high and low power beacons.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: August 25, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Mehmet Yavuz, Sanjiv Nanda, Manoj M. Deshpande, Chirag S. Patel
  • Patent number: 8958795
    Abstract: A method for reducing interference to wireless communication devices is disclosed. A proximity of a wireless communication device to a base station is determined. The proximity of the wireless communication device is compared with a proximity threshold and based on the comparison, access to a femtocell may be granted to a restricted/non-CSG (closed subscriber group) wireless communication device. The method also includes causing a registration response to be sent to the wireless communication device based on the comparison.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: February 17, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yeliz Tokgoz, Chirag S. Patel, Mehmet Yavuz, Sanjiv Nanda, Peter H. Rauber
  • Publication number: 20140235027
    Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.
    Type: Application
    Filed: August 8, 2012
    Publication date: August 21, 2014
    Applicant: International Business Machines Corporation
    Inventors: Harvey Hamel, John Ulrich Knickerbocker, Samuel McKnight, Chirag S. Patel
  • Patent number: 8755644
    Abstract: Method of fabricating a semiconductor die with a microlens associated therewith. More particularly, a method for fabricating a vertical channel guide optical via through a silicon substrate wherein the optical via can contain lens elements, a discrete index gradient guiding pillar and other embodiments. Also disclosed are means for transferring, coupling and or focusing light from an electronic-optical device on the top of a semiconductor substrate through the substrate to a waveguiding medium below the substrate. The high alignment accuracies afforded by standard semiconductor fabrication processes are exploited so as to obviate the need for active alignment of the optical coupling or light guiding elements.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Russell A. Budd, Punit P. Chiniwalla, Chirag S. Patel
  • Patent number: 8405226
    Abstract: A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Chirag S. Patel
  • Patent number: 8328156
    Abstract: Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Peter A. Gruber, Luc Guerin, Chirag S. Patel
  • Publication number: 20120301977
    Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
    Type: Application
    Filed: August 8, 2012
    Publication date: November 29, 2012
    Applicant: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Harm Peter Hofstee, George A. Katopis, John Ulrich Knickerbocker, Robert K. Montoye, Chirag S. Patel
  • Patent number: 8310259
    Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: November 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: Harvey Hamel, John Ulrich Knickerbocker, Samuel McKnight, Chirag S. Patel
  • Patent number: 8295056
    Abstract: A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 23, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul Stephen Andry, Harm Peter Hofstee, George A. Katopis, John Ulrich Knickerbocker, Robert K. Montoye, Chirag S. Patel
  • Patent number: 8290008
    Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 16, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Russell A. Budd, Bing Dang, David Danovitch, Benjamin V. Fasano, Paul Fortier, Luc Guerin, Frank R. Libsch, Sylvain Ouimet, Chirag S. Patel
  • Publication number: 20120249173
    Abstract: A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures.
    Type: Application
    Filed: February 1, 2008
    Publication date: October 4, 2012
    Inventors: HARVEY HAMEL, John Ulrich Knickerbocker, Samuel McKnight, Chirag S. Patel
  • Publication number: 20120248629
    Abstract: A method of fabricating a semiconductor device including forming a micro-chip comprising a thinned-wafer having one or more components fabricated thereon disposed between a carrier and a semiconductor chip, the micro-chip being electrically connected to the semiconductor chip under a higher consumption macro of the semiconductor chip and including a thickness which is less than a thickness of the semiconductor chip, forming an interconnect between the semiconductor chip and the carrier, forming an interconnect between the micro-chip and the semiconductor chip, and forming an interconnect between the micro-chip and the carrier. The micro-chip includes a thinned micro-chip having a thickness of less than 20 microns and the semiconductor chip includes plural semiconductor chips formed as a chip stack. The micro-chip includes a plurality of micro-chips formed on the plural semiconductor chips, such that the semiconductor device is a three-dimensional integrated circuit.
    Type: Application
    Filed: June 13, 2012
    Publication date: October 4, 2012
    Applicant: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Chirag S. Patel
  • Patent number: 8222079
    Abstract: A semiconductor device includes a carrier, a semiconductor chip formed on the carrier, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Chirag S. Patel
  • Publication number: 20120138769
    Abstract: Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.
    Type: Application
    Filed: February 13, 2012
    Publication date: June 7, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bing Dang, Peter A. Gruber, Luc Guerin, Chirag S. Patel
  • Patent number: 8173541
    Abstract: A chip carrier substrate includes a capacitor aperture and a laterally separated via aperture, each located within a substrate. The capacitor aperture is formed with a narrower linewidth and shallower depth than the via aperture incident to a microloading effect within a plasma etch method that is used for simultaneously etching the capacitor aperture and the via aperture within the substrate. Subsequently a capacitor is formed and located within the capacitor aperture and a via is formed and located within the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be contiguous with respect to the capacitor aperture and the via aperture.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Chirag S. Patel
  • Patent number: 8148255
    Abstract: Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: April 3, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bing Dang, Peter A. Gruber, Luc Guerin, Chirag S. Patel
  • Patent number: 8143726
    Abstract: A semiconductor device includes a semiconductor chip, and a micro-chip which is electrically connected to the chip, and includes a thickness which is less than a thickness of the chip.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: March 27, 2012
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Chirag S. Patel