Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.

Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.

Abstract: An intra-metal capacitor unit cell comprises a first electrode and a second electrode formed in the same device layer. A dielectric layer separates the electrodes. The first electrode is substantially surrounded by the second electrode. Misalignment between the first and second electrodes does not substantively alter the capacitance of the unit cell.

Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a a layer of choice.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: A new method of provided for forming in one plane layers of semiconductor material having both high and low dielectric constants. Layers, having selected and preferably non-identical parameters of dielectric constants, are successively deposited interspersed with layers of etch stop material. The layers can be etched, creating openings there-through that can be filled with a layer of choice.

Abstract: An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.

Abstract: A structure and method of fabrication of a capacitor and other devices by providing a semiconductor structure and providing a top insulating layer and conductive features over the semiconductor structure; forming a first conductive layer over the top insulating layer; patterning the first conductive layer to form at least a capacitor bottom plate and a first portion of the first conductive layer; forming a capacitor dielectric layer over the top insulating layer and the capacitor bottom plate and the first portion of the first conductive layer; forming a second conductive layer over the capacitor dielectric layer; and patterning the second conductive layer to form at least a top plate over the bottom plate and a first section of the second conductive layer on the capacitor dielectric layer. The embodiment can further comprise conductive features in the top insulating layer that can underlie the bottom plate, the first portion or/and the first section.

Abstract: A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices.

Abstract: A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

Abstract: A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.

Abstract: In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N2 atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.

Abstract: An improved method to deposit, by atomic layer deposition, ALD, a copper barrier and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a damascene process, for the fabrication of interconnects and inductors, has been developed. A process flow outlining the method of the present invention is as follows: (1) formation of trenches and channels, (2) atomic layer deposition of copper barrier and seed, (3) electroless deposition of copper, (4) chemical mechanical polishing back of excess copper, and (5) barrier deposition, SiN, forming copper interconnects and inductors.

Abstract: A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

Abstract: Methods for forming a metal-insulator-metal (MIM) capacitor using an organic anti-reflective coating (ARC) are described. The first electrode of the MIM capacitor is formed from a first metal layer. The organic ARC is applied, and the second electrode of the MIM capacitor is formed from a second metal layer. The organic ARC is then removed using a nominal clean technique. Because the organic ARC is removed, the performance of the MIM capacitor is improved. Specifically, the breakdown voltage of the MIM capacitor increases and the leakage current decreases.

Abstract: There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.

Abstract: An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing.

Abstract: An improved process for fabricating simultaneously high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, has been developed using single or dual damascene processing. The key advantage is the use of only one additional mask reticle to form both MIM capacitor and resistor, simultaneously. Several current obstacles that exist in BEOL, back end of line, are overcome, namely: (a) the use of two or more photo-masks to make <0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, (c) particles generation concerns during etching, when attempting an etch stop on the bottom MIM plate layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The integrated method overcomes the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing.