Abstract: Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.

Abstract: A switch/router circuit integrates a multi-port memory array with the Media Access Control (MAC) units to facilitate direct transfer of packet payloads to the destination port. The store and forward functions are performed using a single memory cell with multiple pass gates, one pass gate designated for each MAC port. That is, a switch router is implemented using the multi-port memory array such that the number of ports in each memory cell is proportional to the number of MACs integrated in the single monolithic chip. An arbitrator arbitrates between the integrated ports, a lookup table identifies the destination port and a system controller controls all of the integrated elements.

Abstract: Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.

Abstract: Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.

Abstract: The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A DRAM device (200) is disclosed having a plurality of memory cells (208) formed on a substrate (202). Each memory cell (208) includes a transistor (210) having a gate (212), and a storage capacitor (214) having a bottom plate (226) covered with a capacitor dielectric (234). A relatively thin top plate (236) is formed over a number of memory cells (208) in a array portion (204) of the DRAM device (200). The top plate (236) extends to a peripheral array portion (206) where contact is made thereto by metallization (248), by way of a plate contact hole (244). An etch stop (240), formed from the same layer as the gate (212) in the preferred embodiment, is disposed in the peripheral array portion (206) below the plate contact hole (244). The etch stop (240) provides greater flexibility in the plate contact hole etching step, by preventing the plate contact hole (244) from extending through the top plate (236) and to the substrate (202).

Abstract: A method of manufacturing integrated circuits having single and multiple device modes is described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a “by n” input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a “×n” configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a “×2n” configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Abstract: A flash EPROM array (100) and method of manufacture is disclosed. Source regions (118a-118f) are shared between the memory cells (108a,l-108d,n) of row (104a-104d) pairs, and are isolated from one another in the row direction by isolation regions 120. Low resistance source conductor members (122a-122b) extend in the row direction and are formed over the source regions (118a-118f) and make contact therewith in a self-aligned fashion. The architecture allows for source decoding and thus enables user programmable sector erase architecture.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A switch/router circuit integrates a multi-port memory array with the Media Access Control (MAC) units to facilitate direct transfer of packet payloads to the destination port. The store and forward functions are performed using a single memory cell with multiple pass gates, one pass gate designated for each MAC port. That is, a switch router is implemented using the multi-port memory array such that the number of ports in each memory cell is proportional to the number of MACs integrated in the single monolithic chip. An arbitrator arbitrates between the integrated ports, a lookup table identifies the destination port and a system controller controls all of the integrated elements.

Abstract: The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit.

Abstract: According to the first embodiment of the present invention, a pre-charge device is connected to the middle of each complementary bit line. Thus, once activated, the pre-charge device only drives a load equal to half of the RC impedance of the entire bit lines during the pre-charging operation. According to the second embodiment of the present invention, a first pre-charge device is connected to one end of each complementary bit lines and a second pre-charge device is connected approximately to the middle of each complementary bit lines. Once both devices are activated, each device drives a load equal to half of the RC impedance of the entire bit lines, thus reducing the pre-charge time of the bit lines.

Abstract: A sensing circuit (30) for a random access memory (10) is disclosed. A CMOS sense amplifier (32) is coupled between bit line pairs which connected to I/O lines by a passgate (N4/N5). A pair of cross-coupled transistors (N6/N7) activated in synchronism with the passgate (N4/N5) is also disposed between the bit lines. The I/O line pairs each include a pair of cross coupled p-channel transistors (P4/P5). The combined action of the cross-coupled pairs (N6/N7) and (P4/P5) increase the sensing speed of the sensing circuit (30).

Abstract: The present invention provides an apparatus and a method of reducing the time to drive the I/O lines by the sense amplifiers. In one embodiment of the present invention, local sense amplifier segments and associated local I/O lines are provided. The I/O lines are short in length and are connected to the sense amplifiers in the associated sense amplifier segments. The reduction in the length of the local I/O lines reduce the effective RC impedance of the I/O lines. Thus, the local sense amplifiers are smaller and drive the local I/O lines much faster. The present invention further provides global I/O lines connected to the local I/O lines. In a second embodiment of the present invention, the global I/O lines are driven by a second stage amplifier. In a third embodiment of the present invention, one global I/O line is provided for every local I/O line.

Abstract: A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-ship frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.