Abstract: An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).

Abstract: A method of fabricating structures to reduce dielectric damage due to charging is easily incorporated into existing stacked gate fabrication processes. The conductive layers are patterned to form structures which are coupled to the substrate by a current passing device. Each current passing device is isolated from the control gate structures toward the end of the etch process, thereby providing a discharge path for the control gate structures throughout substantially all of the stacked gate etch step. First and second conductive layers are patterned with one or more masks to create stacked gate structures. The multiple masks minimize the exposed area of the second conductive layer during the etch process and so reduce the amount of charging on the gate structures. Each current passing device is preferably an interconnect via coupling the second conductive layer to the first conductive layer.

Abstract: A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures.

Abstract: A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).

Abstract: An SRAM array configuration is disclosed. SRAM cells (102) are arranged in rows and columns. Cell rows (104a-104f) are each driven by a particular word line (132). Cell row pairs (108a and 108b) are supplied with a low power supply voltage (Vss) by a number of Vss connections 116 disposed parallel to the cell rows (104a-104f). The word lines (132) and Vss connections 116 are "strapped" by low resistance word line straps (110b-110e) and Vss straps (112a-112b). Both the word line straps (110b-110e) and the Vss straps (112a-112b) are substantially offset with respect to their associated word lines (132) and Vss connections 116, respectively. The Vss strap offset is accomplished with the use of a Vss line 140 that makes contact with the Vss connections 116 and further includes landing portions 120 which extend in the column direction and make contact with the Vss straps (112a-112b).

Abstract: A static random access memory (SRAM) (10) operating in synchronism with an external clock is disclosed. The synchronous SRAM (10) includes a transparent address circuit (14) for decoding an external address in the set-up time prior to the rising edge of the external clock. A timing and control circuit (18) generates a word line enable (WLE) signal in synchronism with the rising edge of the external clock. When active, WLE activates a word line driver (34), when inactive, WLE equalizes the bit lines. WLE is applied to a first delay circuit (60) to generate a sense signal (SA). SA activates a sense circuit (46) and deactivates the WLE signal. Consecutive pipelined accesses are achieved such that, as an address is decoded, the bit lines are equalizing and the data from the previous address are propagating through a data I/O path (16).

Abstract: A word line select circuit (10) having a rapid de-select operation is disclosed. A group of word lines (12a-12d) is selected in response to a row address and the initial edge of a timing signal (i/RAS) by pulling a group select node (24) to a low power supply voltage (Vss). A particular word line is selected by coupling one of the word line input driver nodes (16a-16d) to the group select node (24). The selected word line is driven to a pump voltage (Vpp) that is greater than the positive supply voltage (Vcc) by a word line driver circuit. Word lines are de-selected on the terminal edge of the i/RAS signal by simultaneously activating de-select transistors (18a-18d) coupled between each input driver node (16a-16d) and Vpp. In the preferred embodiment, the de-select operation also pre-charges the group select node (24) to Vcc-Vtn.

Abstract: Integrated circuits having single and multiple device modes are described. In a preferred random access memory (RAM) embodiment, a first static RAM (SRAM) 10a having a "by n" input/output (I/O) configuration is fabricated adjacent to a second SRAM 10b having the same I/O configuration. An interconnect scheme 14 spans a single device scribe line 18 that separates SRAM 10a from SRAM 10b, and carries address, timing, and control signals between the adjacent SRAMs (10a and 10b). In the event single SRAMs of a ".times.n" configuration are desired, the wafer is sawed along the single device scribe line 18 severing the interconnect scheme 14. In the event multiple device SRAMs of a ".times.2n" configuration are desired, the wafer is sawed into multiple device dies, and the interconnect scheme kept intact.

Abstract: An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).

Abstract: Techniques are provided for protecting the cells of an array against deleterious effects of, for example, photolithography, etching and charge contamination. The cell array is designed to have edge cells modified at layout, or inactive edge cells, or guardrings surrounding the active array to contain the above effects, leaving the active cells highly reliable and with identical behavior.

Abstract: A random access memory (RAM) (10) is disclosed. A network of driver lines (28) extends over a number of core arrays (12a-12p) connecting a control bank 24 with column decode banks (26a and 26b), and the column decode banks (26a and 26b) with sense banks 46 within the core arrays (12a-12p). The driver lines 28 include predecode lines 30 and clock lines 32 for coupling predecode signals and clock signals from the control bank 24 to the column decode banks (26a and 26b). In addition, the driver lines 28 include column select lines 34 and sense driver lines 36 for coupling column select signals and sense amplifier enable signals from the column decode banks (26a and 26b) to the sense banks 46. The sense banks 46 include sense amplifiers 80 that are shared between array quadrants 42 by decoded transfer gate banks (70a and 70b). Advantageous placement of precharge circuits 82 and equalization circuits 86 provides a compact sense bank structure 46.

Abstract: A shared memory graphics accelerator system that provides graphics display data to a display includes a central processing unit for generating graphics display data and graphics commands for processing the display data. An integrated graphics display memory element includes both a graphics accelerator connected to receive display data and graphics commands from the central processing unit and an on-chip frame buffer memory element. The on-chip frame buffer memory element is connected to receive display data from the graphics accelerator via a display data distribution bus. An off-chip frame buffer memory element is also connected to the display data distribution bus to receive display data from the graphics accelerator. The graphics accelerator selectively distributes display data to the on-chip frame buffer memory element and to the off-chip frame buffer memory element based on predetermined display data distribution criteria.

Abstract: A dynamic random access memory cell and method of fabrication thereof are disclosed. An access transistor (10) is formed in a substrate (12). The deposition of a first dielectric layer (20) follows. A plurality of conductive layers (22-30) are deposited, with alternating layers (24 and 28) having a higher dopant concentration than the other layers (22, 26 and 30). A contact hole (32) is etched through the conductive layers (22-30) and the first dielectric layer (20) to the substrate (12). A contact layer (36) is then deposited, making contact with the substrate (12) and each conductive layer (22-30). The conductive layers (22-30) and contact layer (36) are patterned with an isotropic etch selective to the higher doped layers (24 and 28). The resulting structure is a conductive member (42) with a peripheral side surface (44) having inset furrows (40) formed by the selective etching of the higher doped layers (24 and 28). A conformal capacitor dielectric (46) is formed over the conductive structure (42).

Abstract: A dynamic random access memory (DRAM) (10) is disclosed. Memory cell arrays (12) within the DRAM have word lines and bit lines, the bit lines being logically divided into bit line sections (26a-p). Corresponding to each bit line section (26a-p) is a sense/decode section (28a-p) having a fast and slow sense mode of operation. When data are read from a particular bit line section (26a-p) the corresponding sense decode section (28a-p) operates in the fast sense mode while the remaining sense/decode sections (28a-p) operate in the slow sense mode, providing for lower power consumption and/or faster access speeds.

Abstract: A word line driver circuit (10) for driving four word lines (18) is disclosed. In a preferred embodiment, the word line driver circuit (10) includes a decoder circuit (12) for pulling a decode node (20) to a logic low level (Vss) in response to internal row decode signals, a pull-up circuit (14) for pulling the decode node (20) to a logic high (Vcc) to deselect the word lines (18), four transfer transistors (NO) intermediate the decode node (20) and four control nodes (22), four CMOS inverters (18), each driving one word line (18) between a boost voltage and Vss. A PMOS level shifter transistor (P0) is associated with each inverter (18), and has a channel width that is small relative to both the channel widths of the transfer transistors (N0) and to the devices making up the decoder circuit (12), allowing the level shifter transistors (P0) to be overpowered by the decoder circuit (12).

Abstract: A burst dynamic random access memory (DRAM) (10) is disclosed having memory cells arranged in a number of quadrants (22), each quadrant including local I/O lines (24) for accessing the memory cells therein. The local I/O lines (24) of each quadrant are commonly coupled to global I/O lines (26) by tri-state driver banks (30). According to a row address and a first portion of a column address, a row decoding circuit (36) and column decoding circuit (40) couple one set of local I/O lines (24) within each quadrant (22) to selected columns within the quadrants (22). A bank sequencer (48) receives a second portion of the column address and generates burst sequence of different bank select signals. Each bank select signal enables a different set of tri-state driver banks (30). The enabled tri-state driver banks (30) provide a data path between the local I/O lines (24) and the global I/O lines.

Abstract: A timing control circuit (10) is disclosed that provides a timing circuit (12) for controlling the operation of an I/O path circuit (14) in a synchronous static random access memory (SRAM). In a read or write operation, the timing circuit (12) sequentially disables bit line equalization circuits (34), enables sense amplifiers (38), disables I/O line equalization circuits (42), and enables secondary sense amplifiers (44). Further, the timing control (12) initiates a reset operation prior to the completion of the read or write operation. The reset operation includes sequentially enabling the bit line equalization circuits (34), disabling the sense amplifiers (38), enabling the I/O line equalization circuits (42), and disabling the secondary sense amplifiers (44). The timing circuit (12) includes first, second and third delay circuits (20, 22, and 24) to allow for minimum split times for bit line pairs (32) and I/O line pairs (40), and minimum secondary sense amplifier (44) sensing times.

Abstract: The use of nitrogen doped amorphous silicon as an electrode material for a semiconductor integrated circuit is described. A preferred embodiment is a single transistor flash EPROM cell is disclosed having a tunnel dielectric (202), a floating gate (206), an intergate dielectric having three layers (208, 210, 212), and a control gate (218). The floating gate (206) is composed of in-situ nitrogen doped amorphous silicon. Due to the nitrogen doping the floating gate (206) retains its microcrystalline structure under high temperatures, eliminating large grain boundaries in the floating gate (206). As a result, arrays composed of the disclosed EPROM cell have improved memory cell threshold (V.sub.TM) distributions. In addition, silicon oxide grown from the the floating gate (206) has fewer stress induced defects reducing leakage paths that contribute to data retention errors.An alternate embodiment uses nitrogen doped amorphous silicon as the capacitor plates (304 and 306) in a DRAM cell (300).

Abstract: A burst mode static random access memory (SRAM) (10) is disclosed that includes an address transition detect signal (ATD) generating circuit (14) that provides either an asynchronous ATD signal (a-ATD) or a synchronous ATD signal (s-ATD) depending upon the logic state of a mode signal (ATM). A rising edge of the a-ATD signal is generated by a change in address. A falling edge is generated after a predetermined time period according an a-ATD circuit (60) within the ATD generating circuit (14). A falling edge of the s-ATD signal is generated by a rising edge of an internal synchronous clock pulse (CLAT). The rising edge of the s-ATD signal is generated when data are sensed on data lines (40) by an end-of-cycle circuit (20). If ATM is high, the a-ATD signal is used for timing on the SRAM (10). If ATM is low, timing is determined according to the s-ATD signal. An ATD control circuit (16) is provided to generate I/O control signals in response to the ATD signal (either s-ATD or a-ATD).

Abstract: A clamping circuit for clamping a circuit node during an initial circuit powerup interval includes a switching circuit and a switching control circuit. The switching circuit is an N-MOSFET with its drain and source terminals connected to circuit ground and the subject node sought to be clamped, respectively, and its gate terminal connected to the switching control circuit. The switching control circuit includes a number of N-MOSFETs which are interconnected in such a manner as to receive the power supply voltage and generate a switching signal which turns the switching circuit N-MOSFET on during an initial circuit powerup interval to clamp the subject node and then off after the power supply has reached a preselected minimum value. Upon initial circuit powerup, the switching control circuit self-triggers itself to turn the switching circuit on and clamp the subject node at ground potential.