Patents by Inventor Chiung-Wei Lin
Chiung-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11812578Abstract: An enclosure for receiving a plurality of storage components is provided. The enclosure includes a deck, a top cover, a front panel, a stress distributing member, and a pair of component housings. The front panel is disposed between the deck and the top cover disposed over the deck. The stress distributing member traverses an entire width of the deck and is fastened to the deck and the top cover. A front section is defined between the front panel and the stress distributing member. The component housings are arranged in the front section. Each of the component housings has a front end facing outward the enclosure and a back end facing inward the enclosure. Each of the component housings is configured to receive at least a set of one or more of the storage components, and ends of the stress distributing member extend beyond the front ends of the component housings.Type: GrantFiled: November 18, 2022Date of Patent: November 7, 2023Assignee: CHENBRO MICOM CO., LTD.Inventors: Chien-Wen Wang, Han-Chung Chien, Sheng-Chan Lin, Hao-Hsiang Hsu, Chiung-Wei Lin, An-Hsin Chen
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Patent number: 11812575Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.Type: GrantFiled: July 6, 2021Date of Patent: November 7, 2023Assignee: CHENBRO MICOM CO., LTD.Inventors: Chien-Wen Wang, Han-Chung Chien, Sheng-Chan Lin, Hao-Hsiang Hsu, Chiung-Wei Lin, An-Hsin Chen
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Publication number: 20230086839Abstract: An enclosure for receiving a plurality of storage components is provided. The enclosure includes a deck, a top cover, a front panel, a stress distributing member, and a pair of component housings. The front panel is disposed between the deck and the top cover disposed over the deck. The stress distributing member traverses an entire width of the deck and is fastened to the deck and the top cover. A front section is defined between the front panel and the stress distributing member. The component housings are arranged in the front section. Each of the component housings has a front end facing outward the enclosure and a back end facing inward the enclosure. Each of the component housings is configured to receive at least a set of one or more of the storage components, and ends of the stress distributing member extend beyond the front ends of the component housings.Type: ApplicationFiled: November 18, 2022Publication date: March 23, 2023Inventors: CHIEN-WEN WANG, HAN-CHUNG CHIEN, SHENG-CHAN LIN, HAO-HSIANG HSU, CHIUNG-WEI LIN, AN-HSIN CHEN
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Patent number: 11558975Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.Type: GrantFiled: May 19, 2021Date of Patent: January 17, 2023Assignee: CHENBRO MICOM CO., LTD.Inventors: Chien-Wen Wang, Han-Chung Chien, Sheng-Chan Lin, Hao-Hsiang Hsu, Chiung-Wei Lin, An-Hsin Chen
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Publication number: 20210337692Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Inventors: CHIEN-WEN WANG, HAN-CHUNG CHIEN, SHENG-CHAN LIN, HAO-HSIANG HSU, CHIUNG-WEI LIN, AN-HSIN CHEN
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Publication number: 20210274674Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Inventors: CHIEN-WEN WANG, HAN-CHUNG CHIEN, SHENG-CHAN LIN, HAO-HSIANG HSU, CHIUNG-WEI LIN, AN-HSIN CHEN
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Patent number: 10236395Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.Type: GrantFiled: November 24, 2015Date of Patent: March 19, 2019Assignees: Tatung Company, TATUNG UNIVERSITYInventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
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Publication number: 20160079449Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.Type: ApplicationFiled: November 24, 2015Publication date: March 17, 2016Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
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Patent number: 9224893Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.Type: GrantFiled: February 7, 2013Date of Patent: December 29, 2015Assignees: Tatung Company, TATUNG UNIVERSITYInventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
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Publication number: 20140159187Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.Type: ApplicationFiled: February 7, 2013Publication date: June 12, 2014Applicants: TATUNG UNIVERSITY, TATUNG COMPANYInventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
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Patent number: 8535969Abstract: A method for manufacturing a solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores.Type: GrantFiled: June 25, 2012Date of Patent: September 17, 2013Assignees: Tatung Company, Tatung UniversityInventors: Chiung-Wei Lin, Yi-Liang Chen
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Patent number: 8299353Abstract: A solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores. A method of fabricating a solar cell is also provided.Type: GrantFiled: March 9, 2010Date of Patent: October 30, 2012Assignees: Tatung Company, Tatung UniversityInventors: Chiung-Wei Lin, Yi-Liang Chen
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Publication number: 20120258568Abstract: A method for manufacturing a solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores.Type: ApplicationFiled: June 25, 2012Publication date: October 11, 2012Applicants: TATUNG UNIVERSITY, TATUNG COMPANYInventors: Chiung-Wei Lin, Yi-Liang Chen
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Publication number: 20120055542Abstract: A structure of photovoltaic cell for improving conversion efficiency has been disclosed, including a first bandgap layer, a second bandgap layer, a third bandgap layer, a back electrode and a finger electrode, wherein the first bandgap layer is a wafer while the second bandgap layer is a semiconductor film with a thickness of 1˜100 ? and a greater bandgap than one of the first bandgap layer, and the third bandgap layer comprises wide bandgap materials and a greater bandgap than one of the second bandgap layer. Thereby, the lattice mismatch of heterostructures between the first bandgap layer and the third bandgap layer may be solved by the second bandgap layer. Also, the carrier recombination within devices may be decreased and the output photocurrent may thus be enhanced to improve energy conversion efficiency.Type: ApplicationFiled: January 26, 2011Publication date: March 8, 2012Applicants: Tatung Company, Tatung UniversityInventors: Chiung-Wei Lin, Yi-Liang Chen
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Patent number: 8008171Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.Type: GrantFiled: June 9, 2008Date of Patent: August 30, 2011Assignees: Tatung Company, Tatung UniversityInventors: Chiung-Wei Lin, Yi-Liang Chen
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Publication number: 20110168250Abstract: A solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores. A method of fabricating a solar cell is also provided.Type: ApplicationFiled: March 9, 2010Publication date: July 14, 2011Applicants: TATUNG COMPANY, TATUNG UNIVERSITYInventors: Chiung-Wei Lin, Yi-Liang Chen
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Patent number: D976078Type: GrantFiled: July 26, 2021Date of Patent: January 24, 2023Assignee: CHENBRO MICOM CO., LTD.Inventors: Chiung-Wei Lin, Yi-Hsiu Tang
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Patent number: D1023006Type: GrantFiled: June 18, 2021Date of Patent: April 16, 2024Assignee: CHENBRO MICOM CO., LTD.Inventor: Chiung-Wei Lin
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Patent number: D1023007Type: GrantFiled: June 22, 2021Date of Patent: April 16, 2024Assignee: CHENBRO MICOM CO., LTD.Inventor: Chiung-Wei Lin
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Patent number: D1025074Type: GrantFiled: June 18, 2021Date of Patent: April 30, 2024Assignee: CHENBRO MICOM CO., LTD.Inventors: Chiung-Wei Lin, Yi-Chen Chen