Patents by Inventor Chiung-Wei Lin

Chiung-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11812578
    Abstract: An enclosure for receiving a plurality of storage components is provided. The enclosure includes a deck, a top cover, a front panel, a stress distributing member, and a pair of component housings. The front panel is disposed between the deck and the top cover disposed over the deck. The stress distributing member traverses an entire width of the deck and is fastened to the deck and the top cover. A front section is defined between the front panel and the stress distributing member. The component housings are arranged in the front section. Each of the component housings has a front end facing outward the enclosure and a back end facing inward the enclosure. Each of the component housings is configured to receive at least a set of one or more of the storage components, and ends of the stress distributing member extend beyond the front ends of the component housings.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: November 7, 2023
    Assignee: CHENBRO MICOM CO., LTD.
    Inventors: Chien-Wen Wang, Han-Chung Chien, Sheng-Chan Lin, Hao-Hsiang Hsu, Chiung-Wei Lin, An-Hsin Chen
  • Patent number: 11812575
    Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: November 7, 2023
    Assignee: CHENBRO MICOM CO., LTD.
    Inventors: Chien-Wen Wang, Han-Chung Chien, Sheng-Chan Lin, Hao-Hsiang Hsu, Chiung-Wei Lin, An-Hsin Chen
  • Publication number: 20230086839
    Abstract: An enclosure for receiving a plurality of storage components is provided. The enclosure includes a deck, a top cover, a front panel, a stress distributing member, and a pair of component housings. The front panel is disposed between the deck and the top cover disposed over the deck. The stress distributing member traverses an entire width of the deck and is fastened to the deck and the top cover. A front section is defined between the front panel and the stress distributing member. The component housings are arranged in the front section. Each of the component housings has a front end facing outward the enclosure and a back end facing inward the enclosure. Each of the component housings is configured to receive at least a set of one or more of the storage components, and ends of the stress distributing member extend beyond the front ends of the component housings.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 23, 2023
    Inventors: CHIEN-WEN WANG, HAN-CHUNG CHIEN, SHENG-CHAN LIN, HAO-HSIANG HSU, CHIUNG-WEI LIN, AN-HSIN CHEN
  • Patent number: 11558975
    Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 17, 2023
    Assignee: CHENBRO MICOM CO., LTD.
    Inventors: Chien-Wen Wang, Han-Chung Chien, Sheng-Chan Lin, Hao-Hsiang Hsu, Chiung-Wei Lin, An-Hsin Chen
  • Publication number: 20210337692
    Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Inventors: CHIEN-WEN WANG, HAN-CHUNG CHIEN, SHENG-CHAN LIN, HAO-HSIANG HSU, CHIUNG-WEI LIN, AN-HSIN CHEN
  • Publication number: 20210274674
    Abstract: A server system comprises a deck, a front panel arranged on the deck and defining a collecting space; two doors arranged on opposite sides of the deck, and being perpendicular to the front panel; two receiving frame structures arranged between the doors in a back to back arrangement, and configured to receive multiple rows and columns of a plurality of storage drives horizontally, wherein two periphery corridors are each defined between one of the doors and one of the receiving frame structure facing the one door; two circuit boards arranged between the two receiving frame structures, wherein the two circuit boards comprise a plurality of slits, wherein a central corridor is defined between the two circuit boards; a storage cover disposed above the deck over the two periphery corridors, the central corridor, the two receiving frame structures, and the two circuit boards.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Inventors: CHIEN-WEN WANG, HAN-CHUNG CHIEN, SHENG-CHAN LIN, HAO-HSIANG HSU, CHIUNG-WEI LIN, AN-HSIN CHEN
  • Patent number: 10236395
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: March 19, 2019
    Assignees: Tatung Company, TATUNG UNIVERSITY
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Publication number: 20160079449
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Application
    Filed: November 24, 2015
    Publication date: March 17, 2016
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Patent number: 9224893
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: December 29, 2015
    Assignees: Tatung Company, TATUNG UNIVERSITY
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Publication number: 20140159187
    Abstract: A manufacturing method of antireflection substrate structure includes: providing a silicon wafer having a first rough surface; forming an antireflection optical film on the silicon wafer, wherein the antireflection optical film conformally overlays the first rough surface; performing a surface treatment on the antireflection optical film so that the antireflection optical film has a hydrophilic surface, and the hydrophilic surface is relatively far away from the silicon wafer; dropping a colloidal solution on the hydrophilic surface of the antireflection optical film, wherein the colloidal solution includes a solution and multiple nano-balls and the nano-balls are adhered onto the hydrophilic surface; and performing an etching process on the hydrophilic surface of the antireflection optical film by taking the nano-balls as an etching mask so as to form a second rough surface, wherein the roughness of the second rough surface is different from the roughness of the first rough surface.
    Type: Application
    Filed: February 7, 2013
    Publication date: June 12, 2014
    Applicants: TATUNG UNIVERSITY, TATUNG COMPANY
    Inventors: Chiung-Wei Lin, Jheng-Jie Ruan, Yi-Liang Chen, Hsien-Chieh Lin
  • Patent number: 8535969
    Abstract: A method for manufacturing a solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: September 17, 2013
    Assignees: Tatung Company, Tatung University
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Patent number: 8299353
    Abstract: A solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores. A method of fabricating a solar cell is also provided.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: October 30, 2012
    Assignees: Tatung Company, Tatung University
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Publication number: 20120258568
    Abstract: A method for manufacturing a solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores.
    Type: Application
    Filed: June 25, 2012
    Publication date: October 11, 2012
    Applicants: TATUNG UNIVERSITY, TATUNG COMPANY
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Publication number: 20120055542
    Abstract: A structure of photovoltaic cell for improving conversion efficiency has been disclosed, including a first bandgap layer, a second bandgap layer, a third bandgap layer, a back electrode and a finger electrode, wherein the first bandgap layer is a wafer while the second bandgap layer is a semiconductor film with a thickness of 1˜100 ? and a greater bandgap than one of the first bandgap layer, and the third bandgap layer comprises wide bandgap materials and a greater bandgap than one of the second bandgap layer. Thereby, the lattice mismatch of heterostructures between the first bandgap layer and the third bandgap layer may be solved by the second bandgap layer. Also, the carrier recombination within devices may be decreased and the output photocurrent may thus be enhanced to improve energy conversion efficiency.
    Type: Application
    Filed: January 26, 2011
    Publication date: March 8, 2012
    Applicants: Tatung Company, Tatung University
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Patent number: 8008171
    Abstract: Disclosed is a method of providing a poly-Si layer used in fabricating poly-Si TFT's or devices containing poly-Si layers. Particularly, a method utilizing at least one metal plate covering the amorphous silicon layer or the substrate, and applying RTA (Rapid Thermal Annealing) for light illuminating process, then the light converted into heat by the metal plate will further be conducted to the amorphous silicon layer to realize rapid thermal crystallization. Thus the poly-Si layer of the present invention is obtained.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: August 30, 2011
    Assignees: Tatung Company, Tatung University
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Publication number: 20110168250
    Abstract: A solar cell including a photovoltaic layer, a first electrode layer, a second electrode layer, an insulating layer and a light-transparent conductive layer is provided. The photovoltaic layer has a first surface and a second surface. The first electrode layer having at least one gap is disposed on the first surface, wherein the at least one gap exposes a portion of the photovoltaic layer. The second electrode layer is disposed on the second surface. The insulating layer having a plurality of pores is located on the photovoltaic layer exposed by the at least one gap, wherein the holes expose a portion of the photovoltaic layer. The light-transparent conductive layer covers the insulating layer and is connected with the first electrode layer. The transparent electrode is connected with the photovoltaic layer through at least a part of the pores. A method of fabricating a solar cell is also provided.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 14, 2011
    Applicants: TATUNG COMPANY, TATUNG UNIVERSITY
    Inventors: Chiung-Wei Lin, Yi-Liang Chen
  • Patent number: D976078
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 24, 2023
    Assignee: CHENBRO MICOM CO., LTD.
    Inventors: Chiung-Wei Lin, Yi-Hsiu Tang
  • Patent number: D1023006
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: CHENBRO MICOM CO., LTD.
    Inventor: Chiung-Wei Lin
  • Patent number: D1023007
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 16, 2024
    Assignee: CHENBRO MICOM CO., LTD.
    Inventor: Chiung-Wei Lin
  • Patent number: D1025074
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 30, 2024
    Assignee: CHENBRO MICOM CO., LTD.
    Inventors: Chiung-Wei Lin, Yi-Chen Chen