Abstract: Provided is a method for diagnosing and monitoring progression of cancer or effectiveness of a therapeutic treatment. The method includes detecting a methylation level of at least one gene in a biological sample containing circulating free DNA. Also provided are primer pairs and probes for diagnosis or prognosis of cancer in a subject in need thereof.

Abstract: A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Abstract: A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Abstract: A memory chip capable of performing artificial intelligence operation and an operation method thereof are provided. The memory chip includes a memory array, a memory controller, and an artificial intelligence engine. The memory array includes a plurality of memory areas. The memory areas are configured to store digitized input data and weight data. The memory controller is coupled to the memory array via a bus dedicated to the artificial intelligence engine. The artificial intelligence engine accesses the memory array via the memory controller and the bus to obtain the digitized input data and the weight data. The artificial intelligence engine performs a neural network operation based on the digitized input data and the weight data.

Abstract: A self-calibrated system on a chip includes a semiconductor substrate, at least one silicon intellectual property (SIP) circuit including dynamic random access memories (DRAMs), a calibration circuit, and a function circuit, a cyclic oscillator, and a control circuit. Each DRAM has a coarsely-tuned capacitance value and a coarsely-tuned resistance value. The calibration circuit has a finely-tuned capacitance value and a finely-tuned resistance value. The cyclic oscillator transmits an oscillating clock signal to the control circuit to choose and provide the coarsely-tuned capacitance value, the coarsely-tuned resistance value, the finely-tuned capacitance value and the finely-tuned resistance value for the function circuit, thereby adjusting a function parameter.

Abstract: A system-on-chip module for avoiding redundant memory access is provided, comprising at least one microprocessor, a DRAM and a DRAM controller. The DRAM and the microprocessor are integrated and formed in the system-on-chip module commonly. The DRAM controller is electrically connected between the DRAM and the microprocessor, and includes at least one column cache unit such that each microprocessor is able to perform read or write command to the DRAM through its corresponding column cache unit. Compared with the prior arts, the present invention is beneficial to provide better data access quality, efficiency and lower cost and complexity of the system architecture. Thus, the present invention is believed to be applied widely and having greater industrial applicability.

Abstract: A system-on-chip module for avoiding redundant memory access is provided, comprising at least one microprocessor, a DRAM and a DRAM controller. The DRAM and the microprocessor are integrated and formed in the system-on-chip module commonly. The DRAM controller is electrically connected between the DRAM and the microprocessor, and includes at least one column cache unit such that each microprocessor is able to perform read or write command to the DRAM through its corresponding column cache unit. Compared with the prior arts, the present invention is beneficial to provide better data access quality, efficiency and lower cost and complexity of the system architecture. Thus, the present invention is believed to be applied widely and having greater industrial applicability.

Abstract: A self-calibrated system on a chip includes a semiconductor substrate, at least one silicon intellectual property (SIP) circuit including dynamic random access memories (DRAMs), a calibration circuit, and a function circuit, a cyclic oscillator, and a control circuit. Each DRAM has a coarsely-tuned capacitance value and a coarsely-tuned resistance value. The calibration circuit has a finely-tuned capacitance value and a finely-tuned resistance value. The cyclic oscillator transmits an oscillating clock signal to the control circuit to choose and provide the coarsely-tuned capacitance value, the coarsely-tuned resistance value, the finely-tuned capacitance value and the finely-tuned resistance value for the function circuit, thereby adjusting a function parameter.

Abstract: A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.

Abstract: A memory with a processing in memory architecture and an operating method thereof are provided. The memory includes a memory array, a mode register, an artificial intelligence core, and a memory interface. The memory array includes a plurality of memory regions. The mode register stores a plurality of memory mode settings. The memory interface is coupled to the memory array and the mode register, and is externally coupled to a special function processing core. The artificial intelligence core is coupled to the memory array and the mode register. The plurality of memory regions are respectively selectively assigned to the special function processing core or the artificial intelligence core according to the plurality of memory mode settings of the mode register, so that the special function processing core and the artificial intelligence core respectively access different memory regions in the memory array according to the plurality of memory mode settings.

Abstract: A memory chip capable of performing artificial intelligence operation and an operation method thereof are provided. The memory chip includes a memory array, a memory controller, and an artificial intelligence engine. The memory array includes a plurality of memory areas. The memory areas are configured to store digitized input data and weight data. The memory controller is coupled to the memory array via a bus dedicated to the artificial intelligence engine. The artificial intelligence engine accesses the memory array via the memory controller and the bus to obtain the digitized input data and the weight data. The artificial intelligence engine performs a neural network operation based on the digitized input data and the weight data.

Abstract: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures.

Abstract: Stabilization of photolithography process parameters, the photomask being used, and the manufacturing method thereof is provided where a formal pattern layout is combined with a dummy pattern. A photomask is manufactured by utilizing the combined pattern layout so that density changes between the pattern structure layers of the multi-layer semiconductor integrated circuits are minimized.

Abstract: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures.

Abstract: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures.

Abstract: To address problems encountered during the fabrication of a nonvolatile memory cell, such as preventing top oxide loss, preventing contact between the nitride and the polysilicon, and reducing the problem of BD over-diffusion, various fabrication embodiments are used. In one approach, the top dielectric of an ONO structure is formed at the same time as the oxide covering the implanted regions. In another approach, another dielectric structure is formed on the implanted regions and on the top oxide of the charge storage structure. In yet another approach, a cleaning process following ion implantation is performed prior to forming the top oxide of the ONO structure. These approaches also apply to floating gate nonvolatile memories.

Abstract: A method of fabricating a read only memory cell array is described. A patterned film is formed over the substrate to define the predetermined positions of bit lines on the substrate and exposing a plurality of predetermined portions of the substrate. A plurality of field oxide layers is formed on the exposed portions of the substrate to define the positions of channels. After removing the patterned film, ions are implanted into the substrate to form the bit lines by using the field oxide layer as implanting mask. The field oxide layer is removed to form several recesses on the substrate. Thereafter, a gate insulating layer and word lines are formed over the substrate, and the recess channels are formed underneath the gate-insulating layer. The length of the recess channel is large enough to reduce the short channel effect.

Abstract: A method of fabricating a read only memory cell array is described. A patterned film is formed over the substrate to define the predetermined positions of bit lines on the substrate and exposing a plurality of predetermined portions of the substrate. A plurality of field oxide layers is formed on the exposed portions of the substrate to define the positions of channels. After removing the patterned film, ions are implanted into the substrate to form the bit lines by using the field oxide layer as implanting mask. The field oxide layer is removed to form several recesses on the substrate. Thereafter, a gate insulating layer and word lines are formed over the substrate, and the recess channels are formed underneath the gate-insulating layer. The length of the recess channel is large enough to reduce the short channel effect.

Abstract: Roughly described, a device having twin bit floating gate memory cells is fabricated by first providing a substrate having formed thereon, within a memory area, a composite charge storage film and a protective liner layer over the composite film. The memory area further includes oxide features over buried diffusion regions in the substrate, and polysilicon spacers over the composite film against the sidewalls of the oxide features. The method further involves etching an isolation trench through the composite film laterally between two of the oxide features, using the polysilicon spacers as a mask, and forming an insulator in the trench. A gate conductor is then formed overlying both the composite film and the filled isolation trench between the two oxide features.