Abstract: Roughly described, a device having twin bit floating gate memory cells is fabricated by first providing a substrate having formed thereon, within a memory area, a composite charge storage film and a protective liner layer over the composite film. The memory area further includes oxide features over buried diffusion regions in the substrate, and polysilicon spacers over the composite film against the sidewalls of the oxide features. The method further involves etching an isolation trench through the composite film laterally between two of the oxide features, using the polysilicon spacers as a mask, and forming an insulator in the trench. A gate conductor is then formed overlying both the composite film and the filled isolation trench between the two oxide features.

Abstract: An option fuse circuit, which can be viewed as a latch-type option fuse circuit, is manufactured with a standard single-poly CMOS manufacturing process. The option fuse circuit includes a non-volatile memory module for storing a logic bit in a data program status, a data control circuit electrically connected to the non-volatile memory module for controlling operations of the option fuse circuit, and an output circuit electrically connected to the data control circuit for outputting the logic data bit in a data read status.

Abstract: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures.

Abstract: An option fuse circuit, which can be viewed as a latch-type option fuse circuit, is manufactured with a standard single-poly CMOS manufacturing process. The option fuse circuit includes a non-volatile memory module for storing a logic bit in a data program status, a data control circuit electrically connected to the non-volatile memory module for controlling operations of the option fuse circuit, and an output circuit electrically connected to the data control circuit for outputting the logic data bit in a data read status.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: A multi-layer semiconductor integrated circuits enabling stabilizing photolithography process parameters, the photomask being used, and the manufacturing method thereof is provided, which is to provide a formal pattern layout first, and to layout in coordination with a dummy pattern of the regulations, next combine the dummy pattern layout with the formal pattern layout by utilizing the logic operation so that the dummy pattern layout is added within the informal pattern spacing of the formal pattern layout, next to manufacture the photomask by utilizing the fused pattern layout so that it is applicable to various density change of the pattern structure layer of the multi-layer semiconductor integrated circuits with various logic process and further decrease the density variation between multi-layer pattern structures to simply the control of the photolithography process by utilizing the way of adding the dummy pattern layout as well as stabilizing the process.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: The present invention provides a method utilizing dummy patterns to fabricate active region for stabilizing lithographic process. An original pattern layer of active region is first provided, and an attached diffusion layer of dummy patterns is then matched. Logic operations are used to combine the original pattern layer of active region and the attached diffusion layer of dummy patterns together to fill the attached diffusion layer of dummy patterns in more spacious region of the original pattern layer of active region for increasing the pattern density of active region for mask fabrication, hence acquiring a photo mask meeting the requirement of logic device product and applying to logic devices having different pattern densities of active region. Difference of density between products can thus be reduced. The present invention utilizes dummy patterns to simplify and stabilize lithographic process. Simultaneously, lens heating effect can also be reduced.

Abstract: A sensitive test structure for quantitatively detecting antenna effects includes a substrate, an ONO dielectric layer formed over the substrate, an electrode formed over the ONO dielectric layer, and an antenna charge collection electrode (CCE) electrically coupled to the electrode, which is used to collect plasma-induced charge.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

Abstract: A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions. Moreover, the present invention provides two dummy poly gates located on the outside of the poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated together.

Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

Abstract: A salicide integrate solution for embedded virtual-ground memory of the present invention provides a controlled distance between poly gates. In this way, the spacers formed on the sidewalls of the poly gates become self fill-upon spacers, and the surface of the substrate is not exposed. Thus, the salicides will not be formed on the surface of the substrate causing the connection of the buried diffusion regions. Moreover, the present invention provides two dummy poly gates located on the outside of the poly gates, so that the buried diffusion regions on the surface of the embedded virtual-ground memory are covered by the poly gates and self fill-up spacer. Utilizing the present invention, the process of forming salicides on the memory cell region and the peripheral logic region can be integrated together.

Abstract: The present invention is the first one to disclose using of a polysilicon layer in lieu of a silicon nitride (Si3N4) layer, and forming a spacer as a buffering layer by oxidation of polysilicon in oxidation of shallow trenches to protect insulation corners of the shallow trenches (STI corners). This not only omits the process to form and to remove a polymer spacer, but also protects insulation comers of the shallow trenches by forming the polysilicon spacer by oxidation, thereby avoids exposing of the STI comers which results abnormal electricity conductivity.

Abstract: A memory array region and a periphery circuit region are defined on a silicon substrate of a semiconductor wafer. A plurality of gates is formed on the silicon substrate in both the memory array region and the periphery circuit region. A barrier layer and a dielectric layer are formed, respectively, on the semiconductor wafer. Therein, the barrier layer covers the gates and the barrier layer fills a space between two gates. Following that, the dielectric layer atop each gate is removed and the dielectric layer remaining in the space between two gates is aligned to the surface of the gates. A photoresist layer is formed to cover the memory array region followed by an etching process to remove the dielectric layer and the barrier layer down to the surface of the silicon substrate. The photoresist layer and the barrier layer atop the gate in the memory array region are removed. Finally, a salicide process is performed.

Abstract: A method for manufacturing a flash memory device with dual floating gates is disclosed. The method use a self-align etching technique to form dual floating gates by using dual spacers as masks. First of all, a semiconductor substrate having a first insulating layer thereon and a first conductive layer formed over the first insulating layer is provided. Then a second insulating layer is formed and patterned to etch to form a trench therein. Next a dielectric layer is deposited and anisotropically etched to form dual spacers in the trench. After removing the second insulating layer, etching the first conductive layer to expose the first insulating layer, and removing the spacers sequentially, dual floating gates are formed.