Patents by Inventor Chong Ki Kwon
Chong Ki Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8063961Abstract: Provided is a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance. The dual CDS/PxGA circuit comprises: a first sampler for sampling a reset level and a data level of a first pixel; a second sampler for sampling a reset level and a data level of a second pixel; and an operational amplifier for receiving sampling values from the first and second samplers, calculating output signals of the first and second pixels using the sampling values, and amplifying the calculated output signals. Thus, it is possible to reduce a speed of an operational amplifier by using the dual CDS/PxGA structure, reduce power consumption by sharing the operational amplifier, and obtain a variable gain of a wide range by adjusting capacitance using a capacitor array.Type: GrantFiled: August 20, 2008Date of Patent: November 22, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Chong Ki Kwon, Jong Dae Kim
-
Patent number: 7719455Abstract: Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.Type: GrantFiled: August 20, 2008Date of Patent: May 18, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Yi Gyeong Kim, Min Hyung Cho, Chong Ki Kwon
-
Patent number: 7663403Abstract: Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.Type: GrantFiled: November 20, 2007Date of Patent: February 16, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Min Hyung Cho, Kwi Dong Kim, Chong Ki Kwon
-
Patent number: 7576961Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.Type: GrantFiled: January 23, 2008Date of Patent: August 18, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim
-
Patent number: 7554416Abstract: Provided is an LC resonance voltage-controlled oscillator (VCO) used for a multi-band multi-mode wireless transceiver. In order to generate a multi-band frequency, a capacitor bank and a switchable inductor are included in the LC resonance voltage-controlled oscillator. The LC resonance voltage-controlled oscillator employs an adjustable emitter-degeneration negative resistance cell in place of tail current sources in order to compensate for non-uniform oscillation amplitude caused by the capacitor bank and prevent the degradation of a phase noise due to the tail current sources.Type: GrantFiled: October 2, 2006Date of Patent: June 30, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Ja Yol Lee, Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim, Sang Heung Lee, Kyoung Ik Cho
-
Patent number: 7545301Abstract: A delta-sigma modulator having a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; a delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter. More particularly, the delta-sigma modulator has low distortion characteristics suitable for multi-bit fast operation, wherein a feedback signal is delayed by one clock period through the delay circuit and the differential delay circuit.Type: GrantFiled: December 5, 2007Date of Patent: June 9, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Yi Gyeong Kim, Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim
-
Publication number: 20090121909Abstract: Provided are a dynamic element-matching method, a multi-bit Digital-to-Analog Converter (DAC), and a delta-sigma modulator with the multi-bit DAC and delta-sigma DAC with the multi-bit DAC. The dynamic element-matching method relates to preventing periodic signal components (in-band tones) from being generated from a delta-sigma modulator of a delta-sigma Analog-to-Digital Converter (ADC) and a multi-bit DAC used in a delta-sigma DAC. Unit elements are selected in a new sequence according to a simple algorithm every time that each of unit elements is selected once, and thus the unit elements are not periodically used. Consequently, it is possible to prevent in-band tones caused by a conventional Data Weighted Averaging (DWA) algorithm.Type: ApplicationFiled: August 20, 2008Publication date: May 14, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Yi Gyeong KIM, Min Hyung Cho, Chong Ki Kwon
-
Patent number: 7532146Abstract: Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure. In a multiplying digital-to-analog converter (MDAC) used in the multi-bit pipeline ADC, switches are connected between the bottom plates of respective differential capacitors, thereby constantly maintaining a uniform input common mode voltage regardless of an input digital code. Thus, it is possible to improve the operating speed and performance of the MDAC.Type: GrantFiled: September 20, 2007Date of Patent: May 12, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Young Deuk Jeon, Seung Chul Lee, Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim
-
Publication number: 20090086072Abstract: Provided is a dual sampling/pixel gain amplifier (CDS/PxGA) circuit with a shared amplifier, and more particularly, to a dual CDS/PxGA circuit for adjusting a gain of an amplifier based on capacitance. The dual CDS/PxGA circuit comprises: a first sampler for sampling a reset level and a data level of a first pixel; a second sampler for sampling a reset level and a data level of a second pixel; and an operational amplifier for receiving sampling values from the first and second samplers, calculating output signals of the first and second pixels using the sampling values, and amplifying the calculated output signals. Thus, it is possible to reduce a speed of an operational amplifier by using the dual CDS/PxGA structure, reduce power consumption by sharing the operational amplifier, and obtain a variable gain of a wide range by adjusting capacitance using a capacitor array.Type: ApplicationFiled: August 20, 2008Publication date: April 2, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Young Kyun Cho, Young Deuk Jeon, Chong Ki Kwon, Jong Dae Kim
-
Patent number: 7511581Abstract: A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz.Type: GrantFiled: December 5, 2006Date of Patent: March 31, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Ja Yol Lee, Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim, Sang Heung Lee
-
Publication number: 20090072919Abstract: Provided is a voltage-controlled oscillator with a wide oscillation frequency range and linear characteristics, which can linearly change an oscillation frequency versus control voltage due to a variable capacitance range increased by several MOS transistors additionally connected to an LC resonant circuit, and can control the oscillation frequency range by adjusting numbers, widths, lengths and operation regions of the MOS transistors. Thus, the voltage-controlled oscillator with a wide oscillation frequency range and linear control voltage-oscillation frequency characteristics without using a switching device can be implemented.Type: ApplicationFiled: August 20, 2008Publication date: March 19, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Hui Dong Lee, Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim
-
Patent number: 7486216Abstract: Provided is a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode. The ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; an n+1 number of B-bit flash ADCs for receiving an analog signal and converting the analog signal into a digital signal to output the digital signal; an n number of B-bit multiplying digital-to-analog converters (MDACs) for converting a difference between the digital signal output from the B-bit flash ADC and the front-stage output signal into an analog signal to output the analog signal to the next stage; and a mode control circuit for generating n-bit control signals to control the B-bit flash ADC and the B-bit MDAC according to required resolution and operating frequency.Type: GrantFiled: February 16, 2007Date of Patent: February 3, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Seung Chul Lee, Young Deuk Jeon, Kwi Dong Kim, Chong Ki Kwon
-
Multi-bit sigma-delta modulator and digital-to-analog converter with one digital-to-analog capacitor
Patent number: 7388533Abstract: A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.Type: GrantFiled: October 27, 2006Date of Patent: June 17, 2008Assignee: Electronics and Telecommunications Research InstituteInventors: Yi Gyeong Kim, Chong Ki Kwon, Jong Dae Kim, Min Hyung Cho, Seung Chul Lee, Gyu Hyun Kim -
Publication number: 20080136693Abstract: Provided is a delta-sigma modulator including: a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; and delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter.Type: ApplicationFiled: December 5, 2007Publication date: June 12, 2008Inventors: Yi Gyeong KIM, Kwi Dong KIM, Chong Ki KWON, Jong Dae KIM
-
Publication number: 20080136464Abstract: Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit for providing a predetermined current to the differential-signal driving circuit or receiving a predetermined current from the differential-signal driving circuit in response to the common mode voltage. The differential-signal driving circuit includes a common-mode voltage output circuit for connecting the first output node to the second output node and generating the common mode voltage of the differential-signal driving circuit. The differential input signals are received through two bipolar transistors.Type: ApplicationFiled: October 31, 2007Publication date: June 12, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Kwi Dong KIM, Chong Ki Kwon, Jong Dae Kim
-
Publication number: 20080128817Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.Type: ApplicationFiled: January 23, 2008Publication date: June 5, 2008Inventors: Kwi Dong KIM, Chong Ki KWON, Jong Dae KIM
-
Publication number: 20080129338Abstract: Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.Type: ApplicationFiled: November 20, 2007Publication date: June 5, 2008Applicant: Electronics and Telecommunications Research InstituteInventors: Min Hyung CHO, Kwi Dong KIM, Chong Ki KWON
-
Publication number: 20080129567Abstract: Provided is a multi-bit pipeline analog-to-digital converter (ADC) capable of altering an operating mode. The ADC includes: a sample-and-hold amplifier (SHA) for sampling and holding an input analog voltage; an n+1 number of B-bit flash ADCs for receiving an analog signal and converting the analog signal into a digital signal to output the digital signal; an n number of B-bit multiplying digital-to-analog converters (MDACs) for converting a difference between the digital signal output from the B-bit flash ADC and the front-stage output signal into an analog signal to output the analog signal to the next stage; and a mode control circuit for generating n-bit control signals to control the B-bit flash ADC and the B-bit MDAC according to required resolution and operating frequency.Type: ApplicationFiled: February 16, 2007Publication date: June 5, 2008Inventors: Seung Chul Lee, Young Deuk Jeon, Kwi Dong Kim, Chong Ki Kwon
-
Publication number: 20080129576Abstract: Provided is a multi-bit pipeline analog-to-digital converter (ADC) having a merged capacitor switching structure. In a multiplying digital-to-analog converter (MDAC) used in the multi-bit pipeline ADC, switches are connected between the bottom plates of respective differential capacitors, thereby constantly maintaining a uniform input common mode voltage regardless of an input digital code. Thus, it is possible to improve the operating speed and performance of the MDAC.Type: ApplicationFiled: September 20, 2007Publication date: June 5, 2008Inventors: Young Deuk Jeon, Seung Chul Lee, Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim
-
Patent number: 7375504Abstract: Provided is a low-reference-current generator that includes a circuit employing two feedback loops enabling it to operate even at a low voltage, has a high power supply rejection ratio (PSRR) to control power supply noise, and simply forms a voltage without a voltage-to-current converter used in a conventional general reference current generator. The reference current generator includes: a first voltage generator receiving a predetermined current and generating a first voltage that decreases as temperature increases; a second voltage generator generating a second voltage that increases as temperature increases; a first current generator generating a first current corresponding to the first voltage; a second current generator generating a second current corresponding to the second voltage; and a reference current generator receiving the first current and the second current and generating a reference current that is the sum of the first current and the second current.Type: GrantFiled: December 9, 2005Date of Patent: May 20, 2008Assignee: Electronics and Telecommunications Research InstituteInventors: Bong Ki Mheen, Min Hyung Cho, Chong Ki Kwon, Jin Yeong Kang