Abstract: A method of testing an integrated circuit includes providing a bank access sequence received to a register in the integrated circuit, generating a test pattern sequence based on the bank access sequence, and performing a Built-In Self Test (BIST) operation on the integrated circuit based on the generated test pattern sequence.

Abstract: A memory module, a memory unit, and a hub with a non-periodic clock and methods for using the same. An example memory module may include a phased locked loop, receiving an external, periodic clock and generating one or more internal periodic clocks and a plurality of memory units, receiving one of the internal periodic clocks or a non-periodic clock from an external source.

Abstract: A method of entering memory module mounted on a memory system or a plurality of memories mounted on the memory module into a test mode, and a first register and a second register for performing the method are introduced. Each of the memory manufacturers provides a different MRS code for entering the memory into the test mode and a different method of entering the memory into the test mode from one another. As a result, the number of the test MRS is stored in the first register for controlling the memory, and the test MRS codes are programmed into the second register. Additionally, each of the bits stored in the first register used for determining the number of the test MRS corresponds to each of the second registers that store a corresponding test MRS code, respectively.

Abstract: An electronic system having a plurality of dynamic semiconductor memory devices and a refresh method for the same. The system comprises a plurality of dynamic semiconductor memory devices and a controller. Each of the dynamic semiconductor memory devices includes a storage device for storing a designated number designating an order for performing a refresh operation, a refresh enable signal generating circuit for generating a refresh enable signal in response to a refresh control command supplied from the controller and a delaying circuit for delaying the refresh enable signal by different time intervals determined by the designated number.

Abstract: An optoelectronic package (10) includes a base substrate (40), a plurality of solder pads (21) and a can (30). The base substrate includes a mounting seat (41) laminated first and second layer (421,422). The solder pads (21) respectively attach to a top surface (412) and a bottom surface (4212) of the base substrate and are electrically interconnected with each other via conductive material filled the through-holes (411,4223,4213) and conductor trace (45,45′). Optoelectronic components (not shown) are attached to the top surface of the base substrate and make electrical connection with the solder pads. The can includes a transparent device (31), an metal enclosure (32) and a housing (33), which hermetically seals to the base substrate protecting the optoelectronic components.

Abstract: An electronic system having a plurality of dynamic semiconductor memory devices and a refresh method for the same. The system comprises a plurality of dynamic semiconductor memory devices and a controller. Each of the dynamic semiconductor memory devices includes a storage device for storing a designated number designating an order for performing a refresh operation, a refresh enable signal generating circuit for generating a refresh enable signal in response to a refresh control command supplied from the controller and a delaying circuit for delaying the refresh enable signal by different time intervals determined by the designated number.