Patents by Inventor Chong Woo

Chong Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6806552
    Abstract: An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: October 19, 2004
    Assignee: Altera, Corp.
    Inventors: Chong Woo, Clement Szeto, Ting-Wah Wong
  • Patent number: 6751272
    Abstract: In a system that demodulates a frequency modulated signal using a quadrature detector circuit, an apparatus that tunes the output signal to compensate for any offset in the signal includes an offset adjustment circuit and a control circuit. The offset adjustment circuit is operably coupled to the control circuit which may consist of a DAC and a digital logic such as a computer CPU. The control circuit determines a correction signal in response to a sequence of sampled of the system output, and supplies the correction signal to the offset adjustment circuit. The offset adjustment circuit provides an offset correction signal in response to the correction signal, and combines the offset correction signal with the output of the quadrature detector to provide an offset adjusted signal at an output node.
    Type: Grant
    Filed: February 11, 1998
    Date of Patent: June 15, 2004
    Assignee: 3Com Corporation
    Inventors: Lawrence M. Burns, Ravi Ramachandran, David Fisher, Chong Woo, Scott Mitchell
  • Patent number: 6727570
    Abstract: An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: April 27, 2004
    Assignee: Altera Corporation
    Inventor: Chong Woo
  • Publication number: 20030155617
    Abstract: An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.
    Type: Application
    Filed: July 24, 2002
    Publication date: August 21, 2003
    Inventors: Chong Woo, Clement Szeto, Ting-Wah Wong
  • Publication number: 20030155630
    Abstract: An integrated inductor may be formed over a substrate. An aperture may be formed by a backside etch through the semiconductor substrate underneath the integrated inductor. The aperture may then be filled with a dielectric material. As a result of the removal of the underlying substrate material, magnetic and capacitive coupling of the inductor to the substrate may be reduced. In addition, in some cases, the presence of the dielectric may facilitate attachment of the resulting die to a leadframe and package without degrading the inductor's performance and may provide better structural support.
    Type: Application
    Filed: February 21, 2002
    Publication date: August 21, 2003
    Inventor: Chong Woo
  • Patent number: 6020562
    Abstract: Component mounting pads for multi-layer printed circuit boards encompass a smaller area than conventional pads, reducing parasitic capacitance between the pads and a ground plane layer. A number of such pads are arranged to accommodate standard surface-mount component sizes and packages. Further capacitance reductions are achieved by implementing mesh areas or apertures in the board's ground plane opposite the reduced-capacitance pads.
    Type: Grant
    Filed: November 11, 1997
    Date of Patent: February 1, 2000
    Assignee: 3Com Corporation
    Inventors: Lawrence M. Burns, Nicholas Mitchell, Theresa Bradshaw, Chong Woo