Patents by Inventor Chong Zhang

Chong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230408767
    Abstract: A package assembly includes a photonic integrated circuit chip that includes an optical fiber attachment area. The package assembly also includes at least one optical fiber positioned within the optical fiber attachment area. The package assembly also includes a lid structure disposed over the at least one optical fiber. The package assembly also includes a plurality of soldered connections that secure the lid structure to the photonic integrated circuit chip. The plurality of soldered connections are configured to draw the lid structure toward the photonic integrated circuit chip so as to press the lid structure against the at least one optical fiber to mechanically hold the at least one optical fiber against the optical fiber attachment area. The package assembly also includes a package component to which the photonic integrated circuit chip is flip-chip attached after formation of the plurality of soldered connections.
    Type: Application
    Filed: June 14, 2023
    Publication date: December 21, 2023
    Inventors: Derek M. Kita, Chong Zhang, John Fini, Li-Fan Yang
  • Publication number: 20230361534
    Abstract: A device comprises first, second, third and fourth elements fabricated on a common substrate. The first element comprises an active waveguide structure supporting a first optical mode, the second element comprises a passive waveguide structure supporting a second optical mode, the third element, at least partly butt-coupled to the first element, comprises an intermediate waveguide structure supporting intermediate optical modes, and a fourth element comprising TCO material that is attached to the first element. If the first optical mode differs from the second optical mode by more than a predetermined amount, a tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation. No adiabatic transformation occurs between any of the intermediate optical modes and the first optical mode. Mutual alignments of the first, the second, the third, and the fourth elements are defined using lithographic alignment marks.
    Type: Application
    Filed: May 6, 2022
    Publication date: November 9, 2023
    Applicant: Nexus Photonics, Inc.
    Inventors: Chong ZHANG, Minh TRAN, Tin KOMLJENOVIC
  • Patent number: 11808997
    Abstract: A device comprises first, second and third elements fabricated on a common substrate. The first element comprises an active waveguide structure comprising electrically pumped optical source supporting a first optical mode. The second element comprises a passive waveguide structure supporting a second optical mode in at least part of the second element. The third element, at least partly butt-coupled to the first element, comprises an intermediate waveguide structure supporting intermediate optical modes. At least part of the second element supports at least one optical mode that interacts with rare-earth dopants. A tapered waveguide structure in at least one of the second and the third elements facilitates efficient adiabatic transformation between the second optical mode and at least one of the intermediate optical modes. No adiabatic transformation occurs between any of the intermediate optical modes and the first optical mode.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: November 7, 2023
    Assignee: Nexus Photonics Inc.
    Inventors: Minh Tran, Tin Komljenovic, Chong Zhang
  • Publication number: 20230349720
    Abstract: A method for synchronizing neighboring tiles in an electronic map is described. The method includes grouping neighboring tiles of the electronic map into a plurality of tile groups. The method also includes selecting a first tile group and a second tile group that border one another on at least a first tile in the first tile group and a second tile in the second tile group. The method further includes independently optimizing the first tile group and the second tile group if a feature crosses between the first tile group and the second tile group. The method also includes shifting a border of the first tile group and a border of the second tile group to join the first tile and the second tile in the second tile group or the first tile group.
    Type: Application
    Filed: April 29, 2022
    Publication date: November 2, 2023
    Applicants: TOYOTA RESEARCH INSTITUTE, INC., TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hai JIN, Federico BONIARDI, Xipeng WANG, Paul OZOG, Chong ZHANG
  • Publication number: 20230352908
    Abstract: A device comprises first, second and third elements fabricated on a common substrate. The first element comprises an active waveguide structure supporting a first optical mode and at least one of the modal gain control structures. The second element comprises a passive waveguide structure supporting a second optical mode. The third element, at least partly butt-coupled to the first element, comprises an intermediate waveguide structure supporting intermediate optical modes. If the first optical mode differs from the second optical mode by more than a predetermined amount, a tapered waveguide structure in at least one of the second and third elements facilitate efficient adiabatic transformation between the second optical mode and one of the intermediate optical modes. No adiabatic transformation occurs between any of the intermediate optical modes and the first optical mode. Mutual alignments of the first, second and third elements are defined using lithographic alignment marks.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: Nexus Photonics, Inc.
    Inventors: Tin KOMLJENOVIC, Chong ZHANG, Minh TRAN
  • Publication number: 20230352385
    Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.
    Type: Application
    Filed: May 8, 2023
    Publication date: November 2, 2023
    Applicant: Tahoe Research, Ltd.
    Inventors: Yikang DENG, Ying WANG, Cheng XU, Chong ZHANG, Junnan ZHAO
  • Publication number: 20230294143
    Abstract: Provided are a laser cavitation composite ultrasonic cleaning device and cleaning method for a connecting rod, which belong to the technical field of bushing gap cleaning of engine connecting rods. Provided are a laser cavitation composite ultrasonic cleaning device and cleaning method for a connecting rod, the cleaning device comprises a cleaning tank, a bracket, a low-frequency ultrasonic vibrator, a first laser head, and a second laser head; the low-frequency ultrasonic vibrator is located on an outer side of a bottom portion of the cleaning tank; the first laser head is located above the bracket, and the second laser head is located at a lower portion in the cleaning tank. According to the cleaning device, laser light is combined with an ultrasonic wave, cooperated with light path assemblies, and the laser light is focused in a bolt hole and a bushing gap of the connecting rod.
    Type: Application
    Filed: August 1, 2022
    Publication date: September 21, 2023
    Inventors: Guan WANG, Junxian LI, Sihao LIN, Jieyu ZHU, Guohua CHEN, Chong ZHANG
  • Publication number: 20230300912
    Abstract: A session update method, which is applied to a terminal, includes: after a protocol data unit (PDU) session is established, receiving an indication message sent by a network-side device. The indication message includes a slice identifier, and the indication message is used for instructing a terminal to modify and re-establish the PDU session according to the slice identifier, or initiate a PDU session establishment flow.
    Type: Application
    Filed: August 11, 2021
    Publication date: September 21, 2023
    Applicants: CHINA MOBILE COMMUNICATION CO., LTD RESEARCH INSTITUTE, CHINA MOBILE COMMUNICATIONS GROUP CO., LTD.
    Inventors: Xu CHEN, Zhenning HUANG, Chong ZHANG, Yue SONG
  • Patent number: 11762154
    Abstract: A first chip includes a first plurality of optical waveguides exposed at a facet of the first chip. A second chip includes a second plurality of optical waveguides exposed at a facet of the second chip. The second chip includes first and second spacers on opposite sides of the second plurality of optical waveguides. The first and second spacers have respective alignment surfaces oriented substantially parallel to the facet of the second chip at a controlled perpendicular distance away from the facet of the second chip. The second chip is positioned with the alignment surfaces of the first and second spacers contacting the facet of the first chip, and with the second plurality of optical waveguides respectively aligned with the first plurality of optical waveguides. The first and second spacers define and maintain an air gap of at least micrometer-level precision between the first and second pluralities of optical waveguides.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: September 19, 2023
    Assignee: Ayar Labs, Inc.
    Inventors: Manan Raval, Matthew Sysak, Chen Li, Chong Zhang
  • Publication number: 20230290043
    Abstract: Disclosed are a picture generation method performed by a computer device. The method includes: rendering a three-dimensional virtual scene to obtain a scene background rendering map; rendering a first foreground target reported by a first terminal associated with a first client to obtain a first foreground target rendering map; blending the scene background rendering map and the first foreground target rendering map to obtain a first picture, the first picture including the first foreground target displayed in the three-dimensional virtual scene; and providing the first picture to the first terminal associated with the first client for displaying the first picture. A technology of thousand people with thousand faces is achieved, the rendering efficiency can be improved, and the cost is saved.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 14, 2023
    Inventors: Wensheng CAO, Wei Cao, Tangxi Chen, Xiaojie Wang, Lijun Yuan, Chong Zhang, Meng Zhai, Xingyuan Zhu
  • Publication number: 20230280441
    Abstract: Disclosed are a position locking method of an underwater equipment, a terminal device, a system and a medium. The method comprises: acquiring an optical image and a sonar image taken by an underwater equipment; obtaining a target image by synthesizing the optical image and the sonar image, the target image including at least a target object; determining position offset information of the target object according to the target image; and generating position control parameters of the underwater equipment according to the position offset information, and sending position control parameters to the underwater equipment to make the underwater equipment to lock a position according to the position control parameters. The present application greatly reduces operation difficulty of the underwater equipment in turbid or undercurrent water areas.
    Type: Application
    Filed: August 17, 2022
    Publication date: September 7, 2023
    Applicant: SHENZHEN QYSEA TECH CO.,LTD
    Inventors: Wei SUN, ChoJu CHUNG, Chong ZHANG
  • Publication number: 20230266532
    Abstract: A device includes three elements fabricated on a common substrate. The first element includes an active waveguide structure having at least three sub-layers supporting a first optical mode. The second element has a passive waveguide structure supporting a second optical mode, and the third element, butt-coupled to the first element, has an intermediate waveguide structure supporting intermediate optical modes. One sub-layer in the active waveguide structure includes an n-contact layer, another sub-layer includes a p-contact layer, and a third sub-layer includes an active region. A tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the second optical mode and an intermediate optical mode. No adiabatic transformation occurs between that intermediate optical mode and the first optical mode.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Inventors: Chong Zhang, Minh Tran, Tin Komljenovic, Hyun Dai Park
  • Publication number: 20230252758
    Abstract: An image processing method includes: acquiring an image size of an image and original image data of the image; creating a first texture storage area according to the image size, and storing image data of the image into the first texture storage area; creating, according to the image size and a target encoding format, a second texture storage area for storing target image data to be generated, a color encoding format corresponding to the target image data being the target encoding format; and performing, through a shader called by a graphics processor (GPU), encoding format conversion on the original image data stored in the first texture storage area to generate the target image data corresponding to each texture coordinate in the second texture storage area, and storing the target image data corresponding into the each texture coordinate to a corresponding storage location in the second texture storage area.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 10, 2023
    Inventors: Wensheng CAO, Wei CAO, Tangxi CHEN, Lijun YUAN, Xiaojie WANG, Chong ZHANG, Meng ZHAI, Xingyuan ZHU
  • Patent number: 11719883
    Abstract: A device includes three elements fabricated on a common substrate. The first element includes an active waveguide structure having at least three sub-layers supporting a first optical mode. The second element has a passive waveguide structure supporting a second optical mode, and the third element, butt-coupled to the first element, has an intermediate waveguide structure supporting intermediate optical modes. One sub-layer in the active waveguide structure includes an n-contact layer, another sub-layer includes a p-contact layer, and a third sub-layer includes an active region. A tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the second optical mode and an intermediate optical mode. No adiabatic transformation occurs between that intermediate optical mode and the first optical mode.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: August 8, 2023
    Assignee: Nexus Photonics Inc
    Inventors: Chong Zhang, Minh Tran, Tin Komljenovic, Hyun Dai Park
  • Patent number: 11721677
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Chong Zhang, Cheng Xu, Junnan Zhao, Ying Wang, Meizi Jiao
  • Publication number: 20230245385
    Abstract: An interactive method and apparatus based on a virtual scene includes: receiving a virtual scene displaying operation; collecting a first scene image through a first camera coupled to a first terminal; and displaying a virtual environment picture, wherein the virtual environment picture includes a virtual scene and a matting object, the matting object copies a movement of a first object cutout from the first scene image and a movement of a second object cutout from a second scene image, where the second scene image is an image collected by a second camera coupled to a second terminal.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 3, 2023
    Inventor: Chong ZHANG
  • Publication number: 20230238368
    Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Inventors: Chong ZHANG, Cheng XU, Junnan ZHAO, Ying WANG, Meizi JIAO
  • Patent number: 11705389
    Abstract: Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Luke Garner, Liwei Cheng, Lauren Link, Cheng Xu, Ying Wang, Bin Zou, Chong Zhang
  • Patent number: 11702454
    Abstract: The present invention belongs to the field of biotechnology, in particular to a multivalent fusion protein AB-NAC-189, method for producing the same, and uses thereof. The protein AB-NAC-189 is a fusion of a polypeptide segment AB, nascent polypeptide-associated complex (NAC), and a protein 189 corresponding to amino acids 1-189 from the N-terminal of protein HarpinEa. The fusion has the properties of a multivalent plant immune protein, thus it can effectively stimulate the hypersensitive response of tobacco leaves and has good thermal stability. While stimulating the immune response of plants, it can also improve the disease resistance of plants and promote plant growth. The AB-NAC-189 multivalent vaccine shows higher activity per unit concentration, and greater ability to promote growth of wheat and tobacco; meanwhile it can significantly promote chlorophyll synthesis in Goji berry, thereby improving the yield and quality of Goji berries.
    Type: Grant
    Filed: October 17, 2021
    Date of Patent: July 18, 2023
    Assignee: Suzhou Yishuimo Biological Technology Co., LTD
    Inventors: Aiyou Sun, Zhong Wang, Zengying Cai, Qun Yu, Zhiwei Li, Bing Sun, Chong Zhang, Shiyue Miao
  • Publication number: 20230219835
    Abstract: The present invention relates to a high-generation TFT-LCD glass substrate production line. The production line includes a kiln, a large-flow precious metal channel, a tin bath, an annealing kiln, a cutting machine and an unloading machine connected in sequence. The present invention combines high-efficiency melting, clarification and homogenization of molten glass, ultrathin float forming and annealing process technologies of the TFT-LCD glass, which can produce the TFT-LCD glass substrates with large sizes such as 8.5 generations and 10.5/11 generations, which has the advantages of large product size, excellent product performance, coherent process procedures, high production efficiency, high productivity and the like.
    Type: Application
    Filed: April 23, 2021
    Publication date: July 13, 2023
    Inventors: Shou Peng, Chong Zhang, Liangmao Jin, Longyue Jiang, Zhiqiang Cao, Mingliu Zhu, Yuguo Shen