Patents by Inventor Chongyang Wang
Chongyang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12282315Abstract: A method includes determining queue times associated with operations of a sequence recipe. The operations are associated with production of substrates in a substrate processing system. The method further includes generating a schedule based on the queue times. The method further includes transmitting the schedule to a controller of the substrate processing system. The controller is to control the substrate processing system to produce the substrates based on the schedule.Type: GrantFiled: July 11, 2022Date of Patent: April 22, 2025Assignee: Applied Materials, Inc.Inventor: Chongyang Wang
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Patent number: 12254321Abstract: A method of resetting an integrated circuit, includes: generating, in response to a reset signal intended for a first data unit, a synchronous reset signal based on the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period; and generating, in response to a first data signal output by the first data unit, a second data signal based on the synchronous reset signal and the first data signal, and outputting the second data signal to a second data unit. An integrated circuit is also provided.Type: GrantFiled: August 19, 2021Date of Patent: March 18, 2025Assignee: SANECHIPS TECHNOLOGY CO., LTD.Inventors: Chongyang Wang, Chen Lin, Huafeng Xu, Bin Guo
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Publication number: 20250055351Abstract: A motor includes a rotor, a stator, a casing accommodating the rotor and the stator and including an opening in an axial end, an upper bus bar assembly including an upper bus bar holder mounted on an edge of the opening of the casing and an upper bus bar (including an upper bus bar terminal) held on the upper bus bar holder, and a lower bus bar assembly including a lower bus bar holder located on an axially lower side of the upper bus bar holder and a lower bus bar (including a lower bus bar terminal) held on the lower bus bar holder. The upper bus bar terminal and the lower bus bar terminal are electrically connected inside the casing.Type: ApplicationFiled: August 7, 2024Publication date: February 13, 2025Inventor: Chongyang WANG
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Publication number: 20250028304Abstract: A method includes determining a predetermined queue time associated with a process recipe. The predetermined queue time is associated with an amount of time a substrate is at a location prior to being moved from the location. The method further includes causing control of speed associated with one or more components of a substrate processing system based on the predetermined queue time. The control of speed is associated with transfer of the substrate.Type: ApplicationFiled: January 18, 2024Publication date: January 23, 2025Inventor: Chongyang Wang
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Patent number: 12009237Abstract: A method includes generating a queue of a plurality of operations in a sequence recipe, the plurality of operations being associated with substrate processing. The method further includes sorting the plurality of operations in the queue based on a plurality of completion times corresponding to the plurality of operations. The method further includes, for each operation of the plurality of operations in the queue, obtaining a next operation in the queue and setting a virtual time axis to time leap to a corresponding completion time of the next operation until each operation of the plurality of operations in the queue are completed to generate a schedule for the sequence recipe.Type: GrantFiled: September 2, 2022Date of Patent: June 11, 2024Assignee: Applied Materials, Inc.Inventor: Chongyang Wang
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Patent number: 11954061Abstract: A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.Type: GrantFiled: September 23, 2021Date of Patent: April 9, 2024Assignee: BEIJING TSINGMICRO INTELLIGENT TECHNOLOGY CO., LTD.Inventors: Chongyang Wang, Zhen Zhang, Peng Ouyang
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Publication number: 20240036202Abstract: LiDARs and distance measuring methods are provided. In one aspect, a LiDAR includes: a laser emitting device, a control device, a detection device, and a data processing device. The control device is configured to generate a trigger signal based on a time sequence random number. The laser emitting device includes at least one laser and at least one driver coupled with the at least one laser, and a driver is configured to drive a laser coupled to the driver to emit a laser pulse signal according to the trigger signal. The detection device is configured to receive an echo signal of the laser pulse signal reflected by an object and convert the echo signal into an electrical signal. The data processing device is configured to determine distance information of the object based on an emission time of the laser pulse signal and a reception time of the echo signal.Type: ApplicationFiled: October 6, 2023Publication date: February 1, 2024Inventors: Jin YANG, Tianchang GU, Chongyang WANG, Shaoqing XIANG
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Publication number: 20230411881Abstract: A connector, a frame device, and a connector assembly method. Some terminal modules in the connector provided in the present disclosure are removed, or some terminal pairs in the terminal module are removed, so that a quantity of terminal pairs included in the connector is reduced without changing an outline dimension of the connector, thereby ensuring an original docking capability of the connector. In addition, a serial connector may be formed based on different quantities of removed terminal modules or removed terminal pairs. In this way, in the frame device, a user may select a connector of a corresponding specification based on an actual specification of a board, instead of selecting connectors of a high specification uniformly.Type: ApplicationFiled: September 7, 2023Publication date: December 21, 2023Applicant: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Weicheng Gou, Jinhua Ye, Chongyang Wang, Daochun Mo
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Publication number: 20230344126Abstract: This application provides an electronic component, capable of simplifying a structure of an electronic component. The electronic component includes a printed circuit board (PCB) and a cavity. An inner wall of the cavity is provided with at least one groove for fixing the PCB. A first groove in the at least one groove includes a first side wall and a second side wall. The first side wall and the second side wall form an opening of the first groove. A length of the first side wall in a first direction is greater than that of the second side wall. The first direction is parallel to a direction of the opening. The first side wall is provided with at least one first raised part. The first raised part protrudes from the first side wall to the second side wall along a second direction. The second direction is perpendicular to the first direction.Type: ApplicationFiled: June 28, 2023Publication date: October 26, 2023Inventors: Weimin LI, Xinming LIU, Chongyang WANG, Hongzhi ZHANG
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Publication number: 20230325199Abstract: Provided is a method of resetting an integrated circuit, including: generating, in response to a reset signal intended for a first data unit, a synchronous reset signal based on the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period; and generating, in response to a first data signal output by the first data unit, a second data signal based on the synchronous reset signal and the first data signal, and outputting the second data signal to a second data unit. An integrated circuit is also provided.Type: ApplicationFiled: August 19, 2021Publication date: October 12, 2023Inventors: Chongyang WANG, Chen LIN, Huafeng XU, Bin GUO
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Patent number: 11717151Abstract: A method for early diagnosis of keratoconus based on multi-modal data considers a mutual relationship between both eyes using four refractive maps for corneas of the both eyes and absolute corneal elevation data, and combines the deep convolutional network method, the traditional support vector machine (SVM) method in machine learning, and the elevation map enhancement method with adjustable best-fit-sphere (BFS) to identify sensitivity and specificity of a focus and balance the sensitivity and specificity. With multi-dimensional comprehensive judgment of a keratoconus morbidity with a patient as a unit, combined with binocular data including both manual selection features and deep network learning from big data, the diagnosis method has higher robustness and accuracy.Type: GrantFiled: August 5, 2021Date of Patent: August 8, 2023Assignees: SHANGHAI MEDIWORKS PRECISION INSTRUMENTS CO., LTD., EYE AND ENT HOSPITAL OF FUDAN UNIVERSITYInventors: Yang Shen, Xingtao Zhou, Huijie Li, Chongyang Wang, Wenguang Chen, Jing Zhao, Meiyan Li, Yiyong Xian, Haipeng Xu, Lingling Niu, Wuxiao Zhao, Tian Han
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Patent number: 11698877Abstract: Embodiments of the present invention provide a connecting apparatus and a system. The connecting apparatus includes N interconnection units, M line processing units, and X switch processing units, where each interconnection unit is connected to at least one switch processing unit, each switch processing unit is connected to only one interconnection unit, each interconnection unit is connected to the M line processing units, each line processing unit is connected to the N interconnection units, M is a positive integer, N is a positive integer, and X is greater than or equal to N. In addition, the embodiments of the present invention further provide another connecting apparatus and system. According to the foregoing technical solutions, a connecting mode between an LPU and an SPU is relatively flexible.Type: GrantFiled: July 28, 2020Date of Patent: July 11, 2023Assignee: Huawei Technologies Co., Ltd.Inventors: Chongyang Wang, Jun Zhang
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Publication number: 20230190089Abstract: A method for early diagnosis of keratoconus based on multi-modal data considers a mutual relationship between both eyes using four refractive maps for corneas of the both eyes and absolute corneal elevation data, and combines the deep convolutional network method, the traditional support vector machine (SVM) method in machine learning, and the elevation map enhancement method with adjustable best-fit-sphere (BFS) to identify sensitivity and specificity of a focus and balance the sensitivity and specificity. With multi-dimensional comprehensive judgment of a keratoconus morbidity with a patient as a unit, combined with binocular data including both manual selection features and deep network learning from big data, the diagnosis method has higher robustness and accuracy.Type: ApplicationFiled: August 5, 2021Publication date: June 22, 2023Applicants: SHANGHAI MEDIWORKS PRECISION INSTRUMENTS CO., LTD., EYE AND ENT HOSPITAL OF FUDAN UNIVERSITYInventors: Yang SHEN, Xingtao ZHOU, Huijie LI, Chongyang WANG, Wenguang CHEN, Jing ZHAO, Meiyan LI, Yiyong XIAN, Haipeng XU, Lingling NIU, Wuxiao ZHAO, Tian HAN
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Publication number: 20230091656Abstract: A scanning device, a driving condition setting method, and a scanning display module are provided. The scanning device includes two scanning axes capable of vibrating in a first direction and a second direction. The two scanning axes have different frequency characteristics, and the frequency characteristics of the two scanning axes satisfy that a quantity of significant peaks on a frequency characteristic curve does not exceed a set quantity in a set frequency range.Type: ApplicationFiled: August 8, 2022Publication date: March 23, 2023Inventors: Changcheng YAO, Chongyang WANG, Hongbo WANG
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Publication number: 20220415682Abstract: A method includes generating a queue of a plurality of operations in a sequence recipe, the plurality of operations being associated with substrate processing. The method further includes sorting the plurality of operations in the queue based on a plurality of completion times corresponding to the plurality of operations. The method further includes, for each operation of the plurality of operations in the queue, obtaining a next operation in the queue and setting a virtual time axis to time leap to a corresponding completion time of the next operation until each operation of the plurality of operations in the queue are completed to generate a schedule for the sequence recipe.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Inventor: Chongyang Wang
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Publication number: 20220365516Abstract: A method includes determining queue times associated with operations of a sequence recipe. The operations are associated with production of substrates in a substrate processing system. The method further includes generating a schedule based on the queue times. The method further includes transmitting the schedule to a controller of the substrate processing system. The controller is to control the substrate processing system to produce the substrates based on the schedule.Type: ApplicationFiled: July 11, 2022Publication date: November 17, 2022Inventor: Chongyang Wang
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Patent number: 11437254Abstract: A method includes receiving a plurality of operations in a sequence recipe. The plurality of operations are associated with processing a plurality of substrates in a substrate processing system. The method further includes identifying a plurality of completion times corresponding to the plurality of operations. Each completion time of the plurality of completion times corresponds to completion of a respective operation of the plurality of operations. The method further includes simulating the plurality of operations by setting a virtual time axis to each of the plurality of completion times to generate a schedule for the sequence recipe. The method further includes causing, based on the schedule, the plurality of substrates to be processed or performance of a corrective action.Type: GrantFiled: June 24, 2020Date of Patent: September 6, 2022Assignee: Applied Materials, Inc.Inventor: Chongyang Wang
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Patent number: 11385628Abstract: A method includes identifying a bottleneck operation of a plurality of operations in a sequence recipe. The plurality of operations are associated with transporting and processing a plurality of substrates in a substrate processing system. The method further includes determining, based on the bottleneck operation, a takt time for the plurality of substrates. The takt time is an amount of time between a first substrate entering the substrate processing system and a second substrate entering the substrate processing system. The method further includes determining a plurality of queue times. Each of the plurality of queue times corresponds to a respective operation of the plurality of operations. The method further includes causing, based on the takt time and the plurality of queue times, the plurality of substrates to be processed by the substrate processing system.Type: GrantFiled: June 24, 2020Date of Patent: July 12, 2022Assignee: Applied Materials, Inc.Inventor: Chongyang Wang
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Publication number: 20220083495Abstract: A mapping method for a reconfigurable array, including: Si obtaining and analyzing a DDG; providing an initial interval; obtaining a reconfigurable architecture; copying the first adjacency matrix and the second adjacency matrix to form a mapping space; establishing an integer linear programming model, and mapping, with the integer linear programming model, a processing vertex, an intra-cycle edge, and an inter-cycle edge in the DDG, to the mapping space, respectively; obtaining a mapping relationship from the processing vertex and the edge in the DDG to the processing element and the link of extended TS_max layers; and generating configuration information by the mapping relationship modulo the initial interval.Type: ApplicationFiled: September 23, 2021Publication date: March 17, 2022Inventors: Chongyang WANG, Zhen Zhang, Peng OUYANG
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Publication number: 20210405625Abstract: A method includes identifying a bottleneck operation of a plurality of operations in a sequence recipe. The plurality of operations are associated with transporting and processing a plurality of substrates in a substrate processing system. The method further includes determining, based on the bottleneck operation, a takt time for the plurality of substrates. The takt time is an amount of time between a first substrate entering the substrate processing system and a second substrate entering the substrate processing system. The method further includes determining a plurality of queue times. Each of the plurality of queue times corresponds to a respective operation of the plurality of operations. The method further includes causing, based on the takt time and the plurality of queue times, the plurality of substrates to be processed by the substrate processing system.Type: ApplicationFiled: June 24, 2020Publication date: December 30, 2021Inventor: Chongyang Wang